xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/gemini-dlink-dir-685.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * Device Tree file for D-Link DIR-685 Xtreme N Storage Router
3*4882a593Smuzhiyun */
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun/dts-v1/;
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun#include "gemini.dtsi"
8*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun/ {
11*4882a593Smuzhiyun	model = "D-Link DIR-685 Xtreme N Storage Router";
12*4882a593Smuzhiyun	compatible = "dlink,dir-685", "cortina,gemini";
13*4882a593Smuzhiyun	#address-cells = <1>;
14*4882a593Smuzhiyun	#size-cells = <1>;
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun	memory@0 {
17*4882a593Smuzhiyun		/* 128 MB SDRAM in 2 x Hynix HY5DU121622DTP-D43 */
18*4882a593Smuzhiyun		device_type = "memory";
19*4882a593Smuzhiyun		reg = <0x00000000 0x8000000>;
20*4882a593Smuzhiyun	};
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun	chosen {
23*4882a593Smuzhiyun		bootargs = "console=ttyS0,19200n8 root=/dev/sda1 rw rootwait consoleblank=300";
24*4882a593Smuzhiyun		stdout-path = "uart0:19200n8";
25*4882a593Smuzhiyun	};
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun	gpio_keys {
28*4882a593Smuzhiyun		compatible = "gpio-keys";
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun		button-esc {
31*4882a593Smuzhiyun			debounce-interval = <100>;
32*4882a593Smuzhiyun			wakeup-source;
33*4882a593Smuzhiyun			linux,code = <KEY_ESC>;
34*4882a593Smuzhiyun			label = "reset";
35*4882a593Smuzhiyun			/* Collides with LPC_LAD[0], UART DCD, SSP 97RST */
36*4882a593Smuzhiyun			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
37*4882a593Smuzhiyun		};
38*4882a593Smuzhiyun		button-eject {
39*4882a593Smuzhiyun			debounce-interval = <100>;
40*4882a593Smuzhiyun			wakeup-source;
41*4882a593Smuzhiyun			linux,code = <KEY_EJECTCD>;
42*4882a593Smuzhiyun			label = "unmount";
43*4882a593Smuzhiyun			/* Collides with LPC LFRAME, UART RTS, SSP TXD */
44*4882a593Smuzhiyun			gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
45*4882a593Smuzhiyun		};
46*4882a593Smuzhiyun	};
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun	vdisp: regulator {
49*4882a593Smuzhiyun		compatible = "regulator-fixed";
50*4882a593Smuzhiyun		regulator-name = "display-power";
51*4882a593Smuzhiyun		regulator-min-microvolt = <3600000>;
52*4882a593Smuzhiyun		regulator-max-microvolt = <3600000>;
53*4882a593Smuzhiyun		/* Collides with LCD E */
54*4882a593Smuzhiyun		gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>;
55*4882a593Smuzhiyun		enable-active-high;
56*4882a593Smuzhiyun	};
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun	spi {
59*4882a593Smuzhiyun		compatible = "spi-gpio";
60*4882a593Smuzhiyun		#address-cells = <1>;
61*4882a593Smuzhiyun		#size-cells = <0>;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun		/* Collides with IDE pins, that's cool (we do not use them) */
64*4882a593Smuzhiyun		gpio-sck = <&gpio1 5 GPIO_ACTIVE_HIGH>;
65*4882a593Smuzhiyun		gpio-miso = <&gpio1 8 GPIO_ACTIVE_HIGH>;
66*4882a593Smuzhiyun		gpio-mosi = <&gpio1 7 GPIO_ACTIVE_HIGH>;
67*4882a593Smuzhiyun		cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
68*4882a593Smuzhiyun		num-chipselects = <1>;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun		panel: display@0 {
71*4882a593Smuzhiyun			compatible = "dlink,dir-685-panel", "ilitek,ili9322";
72*4882a593Smuzhiyun			reg = <0>;
73*4882a593Smuzhiyun			/* 50 ns min period = 20 MHz */
74*4882a593Smuzhiyun			spi-max-frequency = <20000000>;
75*4882a593Smuzhiyun			vcc-supply = <&vdisp>;
76*4882a593Smuzhiyun			iovcc-supply = <&vdisp>;
77*4882a593Smuzhiyun			vci-supply = <&vdisp>;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun			port {
80*4882a593Smuzhiyun				panel_in: endpoint {
81*4882a593Smuzhiyun					remote-endpoint = <&display_out>;
82*4882a593Smuzhiyun				};
83*4882a593Smuzhiyun			};
84*4882a593Smuzhiyun		};
85*4882a593Smuzhiyun	};
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun	leds {
88*4882a593Smuzhiyun		compatible = "gpio-leds";
89*4882a593Smuzhiyun		led-wps {
90*4882a593Smuzhiyun			label = "dir685:blue:WPS";
91*4882a593Smuzhiyun			/* Collides with ICE */
92*4882a593Smuzhiyun			gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
93*4882a593Smuzhiyun			default-state = "on";
94*4882a593Smuzhiyun			linux,default-trigger = "heartbeat";
95*4882a593Smuzhiyun		};
96*4882a593Smuzhiyun		/*
97*4882a593Smuzhiyun		 * These two LEDs are on the side of the device.
98*4882a593Smuzhiyun		 * For electrical reasons, both LEDs cannot be active
99*4882a593Smuzhiyun		 * at the same time so only blue or orange can be on at
100*4882a593Smuzhiyun		 * one time. Enabling both makes the LED go dark.
101*4882a593Smuzhiyun		 * The LEDs both sit inside the unmount button and the
102*4882a593Smuzhiyun		 * label on the case says "unmount".
103*4882a593Smuzhiyun		 */
104*4882a593Smuzhiyun		led-blue-hd {
105*4882a593Smuzhiyun			label = "dir685:blue:HD";
106*4882a593Smuzhiyun			/* Collides with LPC_SERIRQ, UART DTR, SSP FSC pins */
107*4882a593Smuzhiyun			gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
108*4882a593Smuzhiyun			default-state = "off";
109*4882a593Smuzhiyun			linux,default-trigger = "disk-read";
110*4882a593Smuzhiyun		};
111*4882a593Smuzhiyun		led-orange-hd {
112*4882a593Smuzhiyun			label = "dir685:orange:HD";
113*4882a593Smuzhiyun			/* Collides with LPC_LAD[2], UART DSR, SSP ECLK pins */
114*4882a593Smuzhiyun			gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
115*4882a593Smuzhiyun			default-state = "off";
116*4882a593Smuzhiyun			linux,default-trigger = "disk-write";
117*4882a593Smuzhiyun		};
118*4882a593Smuzhiyun	};
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun	/*
121*4882a593Smuzhiyun	 * This is a Sunon Maglev GM0502PFV2-8 cooling fan @10000 RPM.
122*4882a593Smuzhiyun	 * sensor. It is turned on when the temperature exceeds 46 degrees
123*4882a593Smuzhiyun	 * and turned off when the temperatures goes below 41 degrees
124*4882a593Smuzhiyun	 * (celsius).
125*4882a593Smuzhiyun	 */
126*4882a593Smuzhiyun	fan0: gpio-fan {
127*4882a593Smuzhiyun		compatible = "gpio-fan";
128*4882a593Smuzhiyun		/* Collides with IDE */
129*4882a593Smuzhiyun		gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
130*4882a593Smuzhiyun		gpio-fan,speed-map = <0 0>, <10000 1>;
131*4882a593Smuzhiyun		#cooling-cells = <2>;
132*4882a593Smuzhiyun	};
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun	thermal-zones {
135*4882a593Smuzhiyun		chassis-thermal {
136*4882a593Smuzhiyun			/* Poll every 20 seconds */
137*4882a593Smuzhiyun			polling-delay = <20000>;
138*4882a593Smuzhiyun			/* Poll every 2nd second when cooling */
139*4882a593Smuzhiyun			polling-delay-passive = <2000>;
140*4882a593Smuzhiyun			/*  Use the thermal sensor in the hard drive */
141*4882a593Smuzhiyun			thermal-sensors = <&drive0>;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun			/* Tripping points from the fan.script in the rootfs */
144*4882a593Smuzhiyun			trips {
145*4882a593Smuzhiyun				alert: chassis-alert {
146*4882a593Smuzhiyun					/* At 43 degrees turn on the fan */
147*4882a593Smuzhiyun					temperature = <43000>;
148*4882a593Smuzhiyun					hysteresis = <3000>;
149*4882a593Smuzhiyun					type = "active";
150*4882a593Smuzhiyun				};
151*4882a593Smuzhiyun				crit: chassis-crit {
152*4882a593Smuzhiyun					/* Just shut down at 60 degrees */
153*4882a593Smuzhiyun					temperature = <60000>;
154*4882a593Smuzhiyun					hysteresis = <2000>;
155*4882a593Smuzhiyun					type = "critical";
156*4882a593Smuzhiyun				};
157*4882a593Smuzhiyun			};
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun			cooling-maps {
160*4882a593Smuzhiyun				map0 {
161*4882a593Smuzhiyun					trip = <&alert>;
162*4882a593Smuzhiyun					cooling-device = <&fan0 1 1>;
163*4882a593Smuzhiyun				};
164*4882a593Smuzhiyun			};
165*4882a593Smuzhiyun		};
166*4882a593Smuzhiyun	};
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun	/*
169*4882a593Smuzhiyun	 * The touchpad input is connected to a GPIO bit-banged
170*4882a593Smuzhiyun	 * I2C bus.
171*4882a593Smuzhiyun	 */
172*4882a593Smuzhiyun	gpio-i2c {
173*4882a593Smuzhiyun		compatible = "i2c-gpio";
174*4882a593Smuzhiyun		/* Collides with ICE */
175*4882a593Smuzhiyun		sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
176*4882a593Smuzhiyun		scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
177*4882a593Smuzhiyun		#address-cells = <1>;
178*4882a593Smuzhiyun		#size-cells = <0>;
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun		touchkeys@26 {
181*4882a593Smuzhiyun			compatible = "dlink,dir685-touchkeys";
182*4882a593Smuzhiyun			reg = <0x26>;
183*4882a593Smuzhiyun			interrupt-parent = <&gpio0>;
184*4882a593Smuzhiyun			/* Collides with NAND flash */
185*4882a593Smuzhiyun			interrupts = <17 IRQ_TYPE_EDGE_FALLING>;
186*4882a593Smuzhiyun		};
187*4882a593Smuzhiyun	};
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun	/* This is a RealTek RTL8366RB switch and PHY using SMI over GPIO */
190*4882a593Smuzhiyun	switch {
191*4882a593Smuzhiyun		compatible = "realtek,rtl8366rb";
192*4882a593Smuzhiyun		/* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */
193*4882a593Smuzhiyun		mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
194*4882a593Smuzhiyun		mdio-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
195*4882a593Smuzhiyun		reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
196*4882a593Smuzhiyun		realtek,disable-leds;
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun		switch_intc: interrupt-controller {
199*4882a593Smuzhiyun			/* GPIO 15 provides the interrupt */
200*4882a593Smuzhiyun			interrupt-parent = <&gpio0>;
201*4882a593Smuzhiyun			interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
202*4882a593Smuzhiyun			interrupt-controller;
203*4882a593Smuzhiyun			#address-cells = <0>;
204*4882a593Smuzhiyun			#interrupt-cells = <1>;
205*4882a593Smuzhiyun		};
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun		ports {
208*4882a593Smuzhiyun			#address-cells = <1>;
209*4882a593Smuzhiyun			#size-cells = <0>;
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun			port@0 {
212*4882a593Smuzhiyun				reg = <0>;
213*4882a593Smuzhiyun				label = "lan0";
214*4882a593Smuzhiyun				phy-handle = <&phy0>;
215*4882a593Smuzhiyun			};
216*4882a593Smuzhiyun			port@1 {
217*4882a593Smuzhiyun				reg = <1>;
218*4882a593Smuzhiyun				label = "lan1";
219*4882a593Smuzhiyun				phy-handle = <&phy1>;
220*4882a593Smuzhiyun			};
221*4882a593Smuzhiyun			port@2 {
222*4882a593Smuzhiyun				reg = <2>;
223*4882a593Smuzhiyun				label = "lan2";
224*4882a593Smuzhiyun				phy-handle = <&phy2>;
225*4882a593Smuzhiyun			};
226*4882a593Smuzhiyun			port@3 {
227*4882a593Smuzhiyun				reg = <3>;
228*4882a593Smuzhiyun				label = "lan3";
229*4882a593Smuzhiyun				phy-handle = <&phy3>;
230*4882a593Smuzhiyun			};
231*4882a593Smuzhiyun			port@4 {
232*4882a593Smuzhiyun				reg = <4>;
233*4882a593Smuzhiyun				label = "wan";
234*4882a593Smuzhiyun				phy-handle = <&phy4>;
235*4882a593Smuzhiyun			};
236*4882a593Smuzhiyun			rtl8366rb_cpu_port: port@5 {
237*4882a593Smuzhiyun				reg = <5>;
238*4882a593Smuzhiyun				label = "cpu";
239*4882a593Smuzhiyun				ethernet = <&gmac0>;
240*4882a593Smuzhiyun				phy-mode = "rgmii";
241*4882a593Smuzhiyun				fixed-link {
242*4882a593Smuzhiyun					speed = <1000>;
243*4882a593Smuzhiyun					full-duplex;
244*4882a593Smuzhiyun					pause;
245*4882a593Smuzhiyun				};
246*4882a593Smuzhiyun			};
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun		};
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun		mdio {
251*4882a593Smuzhiyun			compatible = "realtek,smi-mdio";
252*4882a593Smuzhiyun			#address-cells = <1>;
253*4882a593Smuzhiyun			#size-cells = <0>;
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun			phy0: phy@0 {
256*4882a593Smuzhiyun				reg = <0>;
257*4882a593Smuzhiyun				interrupt-parent = <&switch_intc>;
258*4882a593Smuzhiyun				interrupts = <0>;
259*4882a593Smuzhiyun			};
260*4882a593Smuzhiyun			phy1: phy@1 {
261*4882a593Smuzhiyun				reg = <1>;
262*4882a593Smuzhiyun				interrupt-parent = <&switch_intc>;
263*4882a593Smuzhiyun				interrupts = <1>;
264*4882a593Smuzhiyun			};
265*4882a593Smuzhiyun			phy2: phy@2 {
266*4882a593Smuzhiyun				reg = <2>;
267*4882a593Smuzhiyun				interrupt-parent = <&switch_intc>;
268*4882a593Smuzhiyun				interrupts = <2>;
269*4882a593Smuzhiyun			};
270*4882a593Smuzhiyun			phy3: phy@3 {
271*4882a593Smuzhiyun				reg = <3>;
272*4882a593Smuzhiyun				interrupt-parent = <&switch_intc>;
273*4882a593Smuzhiyun				interrupts = <3>;
274*4882a593Smuzhiyun			};
275*4882a593Smuzhiyun			phy4: phy@4 {
276*4882a593Smuzhiyun				reg = <4>;
277*4882a593Smuzhiyun				interrupt-parent = <&switch_intc>;
278*4882a593Smuzhiyun				interrupts = <12>;
279*4882a593Smuzhiyun			};
280*4882a593Smuzhiyun		};
281*4882a593Smuzhiyun	};
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun	soc {
284*4882a593Smuzhiyun		flash@30000000 {
285*4882a593Smuzhiyun			/*
286*4882a593Smuzhiyun			 * Flash access collides with the Chip Enable signal for
287*4882a593Smuzhiyun			 * the display panel, that reuse the parallel flash Chip
288*4882a593Smuzhiyun			 * Select 1 (CS1). We switch the pin control state so we
289*4882a593Smuzhiyun			 * enable these pins for flash access only when we need
290*4882a593Smuzhiyun			 * then, and when disabled they can be used for GPIO which
291*4882a593Smuzhiyun			 * is what the display panel needs.
292*4882a593Smuzhiyun			 */
293*4882a593Smuzhiyun			status = "okay";
294*4882a593Smuzhiyun			pinctrl-names = "enabled", "disabled";
295*4882a593Smuzhiyun			pinctrl-0 = <&pflash_default_pins>;
296*4882a593Smuzhiyun			pinctrl-1 = <&pflash_disabled_pins>;
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun			/* 32MB of flash */
299*4882a593Smuzhiyun			reg = <0x30000000 0x02000000>;
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun			partitions {
302*4882a593Smuzhiyun				compatible = "fixed-partitions";
303*4882a593Smuzhiyun				#address-cells = <1>;
304*4882a593Smuzhiyun				#size-cells = <1>;
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun				/*
307*4882a593Smuzhiyun				 * This "RedBoot" is the Storlink derivative.
308*4882a593Smuzhiyun				 */
309*4882a593Smuzhiyun				partition@0 {
310*4882a593Smuzhiyun					label = "RedBoot";
311*4882a593Smuzhiyun					reg = <0x00000000 0x00040000>;
312*4882a593Smuzhiyun					read-only;
313*4882a593Smuzhiyun				};
314*4882a593Smuzhiyun				/*
315*4882a593Smuzhiyun				 * This firmware image contains the kernel catenated
316*4882a593Smuzhiyun				 * with the squashfs root filesystem. For some reason
317*4882a593Smuzhiyun				 * this is called "upgrade" on the vendor system.
318*4882a593Smuzhiyun				 */
319*4882a593Smuzhiyun				partition@40000 {
320*4882a593Smuzhiyun					label = "upgrade";
321*4882a593Smuzhiyun					reg = <0x00040000 0x01f40000>;
322*4882a593Smuzhiyun					read-only;
323*4882a593Smuzhiyun				};
324*4882a593Smuzhiyun				/* RGDB, Residental Gateway Database? */
325*4882a593Smuzhiyun				partition@1f80000 {
326*4882a593Smuzhiyun					label = "rgdb";
327*4882a593Smuzhiyun					reg = <0x01f80000 0x00040000>;
328*4882a593Smuzhiyun					read-only;
329*4882a593Smuzhiyun				};
330*4882a593Smuzhiyun				/*
331*4882a593Smuzhiyun				 * This partition contains MAC addresses for WAN,
332*4882a593Smuzhiyun				 * WLAN and LAN, and the country code (for wireless
333*4882a593Smuzhiyun				 * I guess).
334*4882a593Smuzhiyun				 */
335*4882a593Smuzhiyun				partition@1fc0000 {
336*4882a593Smuzhiyun					label = "nvram";
337*4882a593Smuzhiyun					reg = <0x01fc0000 0x00020000>;
338*4882a593Smuzhiyun					read-only;
339*4882a593Smuzhiyun				};
340*4882a593Smuzhiyun				partition@1fe0000 {
341*4882a593Smuzhiyun					label = "LangPack";
342*4882a593Smuzhiyun					reg = <0x01fe0000 0x00020000>;
343*4882a593Smuzhiyun					read-only;
344*4882a593Smuzhiyun				};
345*4882a593Smuzhiyun			};
346*4882a593Smuzhiyun		};
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun		syscon: syscon@40000000 {
349*4882a593Smuzhiyun			pinctrl {
350*4882a593Smuzhiyun				/*
351*4882a593Smuzhiyun				 * gpio0bgrp cover line 5, 6 used by TK I2C
352*4882a593Smuzhiyun				 * gpio0bgrp cover line 7 used by WPS LED
353*4882a593Smuzhiyun				 * gpio0cgrp cover line 8, 13 used by keys
354*4882a593Smuzhiyun				 *           and 11, 12 used by the HD LEDs
355*4882a593Smuzhiyun				 *           and line 14, 15 used by RTL8366
356*4882a593Smuzhiyun				 *           RESET and phy ready
357*4882a593Smuzhiyun				 * gpio0egrp cover line 16 used by VDISP
358*4882a593Smuzhiyun				 * gpio0fgrp cover line 17 used by TK IRQ
359*4882a593Smuzhiyun				 * gpio0ggrp cover line 20 used by panel CS
360*4882a593Smuzhiyun				 * gpio0hgrp cover line 21,22 used by RTL8366RB MDIO
361*4882a593Smuzhiyun				 */
362*4882a593Smuzhiyun				gpio0_default_pins: pinctrl-gpio0 {
363*4882a593Smuzhiyun					mux {
364*4882a593Smuzhiyun						function = "gpio0";
365*4882a593Smuzhiyun						groups = "gpio0bgrp",
366*4882a593Smuzhiyun						"gpio0cgrp",
367*4882a593Smuzhiyun						"gpio0egrp",
368*4882a593Smuzhiyun						"gpio0fgrp",
369*4882a593Smuzhiyun						"gpio0hgrp";
370*4882a593Smuzhiyun					};
371*4882a593Smuzhiyun				};
372*4882a593Smuzhiyun				/*
373*4882a593Smuzhiyun				 * gpio1bgrp cover line 5,8,7 used by panel SPI
374*4882a593Smuzhiyun				 * also line 6 used by the fan
375*4882a593Smuzhiyun				 *
376*4882a593Smuzhiyun				 */
377*4882a593Smuzhiyun				gpio1_default_pins: pinctrl-gpio1 {
378*4882a593Smuzhiyun					mux {
379*4882a593Smuzhiyun						function = "gpio1";
380*4882a593Smuzhiyun						groups = "gpio1bgrp";
381*4882a593Smuzhiyun					};
382*4882a593Smuzhiyun				};
383*4882a593Smuzhiyun				/*
384*4882a593Smuzhiyun				 * These GPIO groups will be mapped in over some
385*4882a593Smuzhiyun				 * of the flash pins when the flash is not in
386*4882a593Smuzhiyun				 * active use.
387*4882a593Smuzhiyun				 */
388*4882a593Smuzhiyun				pflash_disabled_pins: pinctrl-pflash-disabled {
389*4882a593Smuzhiyun					mux {
390*4882a593Smuzhiyun						function = "gpio0";
391*4882a593Smuzhiyun						groups = "gpio0ggrp", "gpio0igrp", "gpio0jgrp",
392*4882a593Smuzhiyun							 "gpio0kgrp";
393*4882a593Smuzhiyun					};
394*4882a593Smuzhiyun				};
395*4882a593Smuzhiyun				pinctrl-gmii {
396*4882a593Smuzhiyun					mux {
397*4882a593Smuzhiyun						function = "gmii";
398*4882a593Smuzhiyun						groups = "gmii_gmac0_grp";
399*4882a593Smuzhiyun					};
400*4882a593Smuzhiyun					conf0 {
401*4882a593Smuzhiyun						pins = "V8 GMAC0 RXDV", "T10 GMAC1 RXDV",
402*4882a593Smuzhiyun						     "Y7 GMAC0 RXC", "Y11 GMAC1 RXC",
403*4882a593Smuzhiyun						     "T8 GMAC0 TXEN", "W11 GMAC1 TXEN",
404*4882a593Smuzhiyun						     "U8 GMAC0 TXC", "V11 GMAC1 TXC",
405*4882a593Smuzhiyun						     "W8 GMAC0 RXD0", "V9 GMAC0 RXD1",
406*4882a593Smuzhiyun						     "Y8 GMAC0 RXD2", "U9 GMAC0 RXD3",
407*4882a593Smuzhiyun						     "T7 GMAC0 TXD0", "U6 GMAC0 TXD1",
408*4882a593Smuzhiyun						     "V7 GMAC0 TXD2", "U7 GMAC0 TXD3",
409*4882a593Smuzhiyun						     "Y12 GMAC1 RXD0", "V12 GMAC1 RXD1",
410*4882a593Smuzhiyun						     "T11 GMAC1 RXD2", "W12 GMAC1 RXD3",
411*4882a593Smuzhiyun						     "U10 GMAC1 TXD0", "Y10 GMAC1 TXD1",
412*4882a593Smuzhiyun						     "W10 GMAC1 TXD2", "T9 GMAC1 TXD3";
413*4882a593Smuzhiyun						skew-delay = <7>;
414*4882a593Smuzhiyun					};
415*4882a593Smuzhiyun					/* Set up drive strength on GMAC0 to 16 mA */
416*4882a593Smuzhiyun					conf1 {
417*4882a593Smuzhiyun						groups = "gmii_gmac0_grp";
418*4882a593Smuzhiyun						drive-strength = <16>;
419*4882a593Smuzhiyun					};
420*4882a593Smuzhiyun				};
421*4882a593Smuzhiyun			};
422*4882a593Smuzhiyun		};
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun		sata: sata@46000000 {
425*4882a593Smuzhiyun			cortina,gemini-ata-muxmode = <0>;
426*4882a593Smuzhiyun			cortina,gemini-enable-sata-bridge;
427*4882a593Smuzhiyun			status = "okay";
428*4882a593Smuzhiyun		};
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun		gpio0: gpio@4d000000 {
431*4882a593Smuzhiyun			pinctrl-names = "default";
432*4882a593Smuzhiyun			pinctrl-0 = <&gpio0_default_pins>;
433*4882a593Smuzhiyun		};
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun		gpio1: gpio@4e000000 {
436*4882a593Smuzhiyun			pinctrl-names = "default";
437*4882a593Smuzhiyun			pinctrl-0 = <&gpio1_default_pins>;
438*4882a593Smuzhiyun		};
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun		pci@50000000 {
441*4882a593Smuzhiyun			status = "okay";
442*4882a593Smuzhiyun			interrupt-map-mask = <0xf800 0 0 7>;
443*4882a593Smuzhiyun			interrupt-map =
444*4882a593Smuzhiyun				<0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
445*4882a593Smuzhiyun				<0x4800 0 0 2 &pci_intc 1>,
446*4882a593Smuzhiyun				<0x4800 0 0 3 &pci_intc 2>,
447*4882a593Smuzhiyun				<0x4800 0 0 4 &pci_intc 3>,
448*4882a593Smuzhiyun				<0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
449*4882a593Smuzhiyun				<0x5000 0 0 2 &pci_intc 2>,
450*4882a593Smuzhiyun				<0x5000 0 0 3 &pci_intc 3>,
451*4882a593Smuzhiyun				<0x5000 0 0 4 &pci_intc 0>,
452*4882a593Smuzhiyun				<0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
453*4882a593Smuzhiyun				<0x5800 0 0 2 &pci_intc 3>,
454*4882a593Smuzhiyun				<0x5800 0 0 3 &pci_intc 0>,
455*4882a593Smuzhiyun				<0x5800 0 0 4 &pci_intc 1>,
456*4882a593Smuzhiyun				<0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
457*4882a593Smuzhiyun				<0x6000 0 0 2 &pci_intc 0>,
458*4882a593Smuzhiyun				<0x6000 0 0 3 &pci_intc 1>,
459*4882a593Smuzhiyun				<0x6000 0 0 4 &pci_intc 2>;
460*4882a593Smuzhiyun		};
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun		ethernet@60000000 {
463*4882a593Smuzhiyun			status = "okay";
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun			ethernet-port@0 {
466*4882a593Smuzhiyun				phy-mode = "rgmii";
467*4882a593Smuzhiyun				fixed-link {
468*4882a593Smuzhiyun					speed = <1000>;
469*4882a593Smuzhiyun					full-duplex;
470*4882a593Smuzhiyun					pause;
471*4882a593Smuzhiyun				};
472*4882a593Smuzhiyun			};
473*4882a593Smuzhiyun			ethernet-port@1 {
474*4882a593Smuzhiyun				/* Not used in this platform */
475*4882a593Smuzhiyun			};
476*4882a593Smuzhiyun		};
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun		ide@63000000 {
479*4882a593Smuzhiyun			status = "okay";
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun			/*
482*4882a593Smuzhiyun			 * This drive may have a temperature sensor with a
483*4882a593Smuzhiyun			 * thermal zone we can use for thermal control of the
484*4882a593Smuzhiyun			 * chassis temperature using the fan.
485*4882a593Smuzhiyun			 */
486*4882a593Smuzhiyun			drive0: ide-port@0 {
487*4882a593Smuzhiyun				reg = <0>;
488*4882a593Smuzhiyun				#thermal-sensor-cells = <0>;
489*4882a593Smuzhiyun			};
490*4882a593Smuzhiyun		};
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun		display-controller@6a000000 {
493*4882a593Smuzhiyun			status = "okay";
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun			port@0 {
496*4882a593Smuzhiyun				reg = <0>;
497*4882a593Smuzhiyun				display_out: endpoint {
498*4882a593Smuzhiyun					remote-endpoint = <&panel_in>;
499*4882a593Smuzhiyun				};
500*4882a593Smuzhiyun			};
501*4882a593Smuzhiyun		};
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun		usb@68000000 {
504*4882a593Smuzhiyun			status = "okay";
505*4882a593Smuzhiyun		};
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun		usb@69000000 {
508*4882a593Smuzhiyun			status = "okay";
509*4882a593Smuzhiyun		};
510*4882a593Smuzhiyun	};
511*4882a593Smuzhiyun};
512