1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Samsung XYREF5260 board device tree source 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2013 Samsung Electronics Co., Ltd. 6*4882a593Smuzhiyun * http://www.samsung.com 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/dts-v1/; 10*4882a593Smuzhiyun#include "exynos5260.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun model = "Samsung XYREF5260 board based on Exynos5260"; 14*4882a593Smuzhiyun compatible = "samsung,xyref5260", "samsung,exynos5260", "samsung,exynos5"; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun memory@20000000 { 17*4882a593Smuzhiyun device_type = "memory"; 18*4882a593Smuzhiyun reg = <0x20000000 0x80000000>; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun chosen { 22*4882a593Smuzhiyun stdout-path = "serial2:115200n8"; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun fin_pll: xxti { 26*4882a593Smuzhiyun compatible = "fixed-clock"; 27*4882a593Smuzhiyun clock-frequency = <24000000>; 28*4882a593Smuzhiyun clock-output-names = "fin_pll"; 29*4882a593Smuzhiyun #clock-cells = <0>; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun xrtcxti: xrtcxti { 33*4882a593Smuzhiyun compatible = "fixed-clock"; 34*4882a593Smuzhiyun clock-frequency = <32768>; 35*4882a593Smuzhiyun clock-output-names = "xrtcxti"; 36*4882a593Smuzhiyun #clock-cells = <0>; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun}; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun&pinctrl_0 { 41*4882a593Smuzhiyun hdmi_hpd_irq: hdmi-hpd-irq { 42*4882a593Smuzhiyun samsung,pins = "gpx3-7"; 43*4882a593Smuzhiyun samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; 44*4882a593Smuzhiyun samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; 45*4882a593Smuzhiyun samsung,pin-drv = <EXYNOS5260_PIN_DRV_LV1>; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun}; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun&uart0 { 50*4882a593Smuzhiyun status = "okay"; 51*4882a593Smuzhiyun}; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun&uart1 { 54*4882a593Smuzhiyun status = "okay"; 55*4882a593Smuzhiyun}; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun&uart2 { 58*4882a593Smuzhiyun status = "okay"; 59*4882a593Smuzhiyun}; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun&uart3 { 62*4882a593Smuzhiyun status = "okay"; 63*4882a593Smuzhiyun}; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun&mmc_0 { 66*4882a593Smuzhiyun status = "okay"; 67*4882a593Smuzhiyun broken-cd; 68*4882a593Smuzhiyun cap-mmc-highspeed; 69*4882a593Smuzhiyun supports-hs200-mode; /* 200 MHz */ 70*4882a593Smuzhiyun card-detect-delay = <200>; 71*4882a593Smuzhiyun samsung,dw-mshc-ciu-div = <3>; 72*4882a593Smuzhiyun samsung,dw-mshc-sdr-timing = <0 4>; 73*4882a593Smuzhiyun samsung,dw-mshc-ddr-timing = <0 2>; 74*4882a593Smuzhiyun pinctrl-names = "default"; 75*4882a593Smuzhiyun pinctrl-0 = <&sd0_rdqs &sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; 76*4882a593Smuzhiyun bus-width = <8>; 77*4882a593Smuzhiyun}; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun&mmc_2 { 80*4882a593Smuzhiyun status = "okay"; 81*4882a593Smuzhiyun cap-sd-highspeed; 82*4882a593Smuzhiyun card-detect-delay = <200>; 83*4882a593Smuzhiyun samsung,dw-mshc-ciu-div = <3>; 84*4882a593Smuzhiyun samsung,dw-mshc-sdr-timing = <2 3>; 85*4882a593Smuzhiyun samsung,dw-mshc-ddr-timing = <1 2>; 86*4882a593Smuzhiyun pinctrl-names = "default"; 87*4882a593Smuzhiyun pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; 88*4882a593Smuzhiyun bus-width = <4>; 89*4882a593Smuzhiyun disable-wp; 90*4882a593Smuzhiyun}; 91