1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Samsung's Exynos3250 based ARTIK5 evaluation board device tree source 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2016 Samsung Electronics Co., Ltd. 6*4882a593Smuzhiyun * http://www.samsung.com 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Device tree source file for Samsung's ARTIK5 evaluation board 9*4882a593Smuzhiyun * which is based on Samsung Exynos3250 SoC. 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/dts-v1/; 13*4882a593Smuzhiyun#include "exynos3250-artik5.dtsi" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun/ { 16*4882a593Smuzhiyun model = "Samsung ARTIK5 evaluation board"; 17*4882a593Smuzhiyun compatible = "samsung,artik5-eval", "samsung,artik5", 18*4882a593Smuzhiyun "samsung,exynos3250", "samsung,exynos3"; 19*4882a593Smuzhiyun}; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun&mshc_2 { 22*4882a593Smuzhiyun cap-sd-highspeed; 23*4882a593Smuzhiyun disable-wp; 24*4882a593Smuzhiyun vqmmc-supply = <&ldo3_reg>; 25*4882a593Smuzhiyun card-detect-delay = <200>; 26*4882a593Smuzhiyun clock-frequency = <100000000>; 27*4882a593Smuzhiyun max-frequency = <100000000>; 28*4882a593Smuzhiyun samsung,dw-mshc-ciu-div = <1>; 29*4882a593Smuzhiyun samsung,dw-mshc-sdr-timing = <0 1>; 30*4882a593Smuzhiyun samsung,dw-mshc-ddr-timing = <1 2>; 31*4882a593Smuzhiyun pinctrl-names = "default"; 32*4882a593Smuzhiyun pinctrl-0 = <&sd2_cmd &sd2_clk &sd2_cd &sd2_bus1 &sd2_bus4>; 33*4882a593Smuzhiyun bus-width = <4>; 34*4882a593Smuzhiyun status = "okay"; 35*4882a593Smuzhiyun}; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun&serial_2 { 38*4882a593Smuzhiyun status = "okay"; 39*4882a593Smuzhiyun}; 40