1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device tree for Energy Micro EFM32 Giant Gecko SoC. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Documentation available from 6*4882a593Smuzhiyun * http://www.silabs.com/Support%20Documents/TechnicalDocs/EFM32GG-RM.pdf 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include "armv7-m.dtsi" 10*4882a593Smuzhiyun#include "dt-bindings/clock/efm32-cmu.h" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun #address-cells = <1>; 14*4882a593Smuzhiyun #size-cells = <1>; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun aliases { 17*4882a593Smuzhiyun i2c0 = &i2c0; 18*4882a593Smuzhiyun i2c1 = &i2c1; 19*4882a593Smuzhiyun serial0 = &uart0; 20*4882a593Smuzhiyun serial1 = &uart1; 21*4882a593Smuzhiyun serial2 = &uart2; 22*4882a593Smuzhiyun serial3 = &uart3; 23*4882a593Smuzhiyun serial4 = &uart4; 24*4882a593Smuzhiyun spi0 = &spi0; 25*4882a593Smuzhiyun spi1 = &spi1; 26*4882a593Smuzhiyun spi2 = &spi2; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun soc { 30*4882a593Smuzhiyun adc: adc@40002000 { 31*4882a593Smuzhiyun compatible = "energymicro,efm32-adc"; 32*4882a593Smuzhiyun reg = <0x40002000 0x400>; 33*4882a593Smuzhiyun interrupts = <7>; 34*4882a593Smuzhiyun clocks = <&cmu clk_HFPERCLKADC0>; 35*4882a593Smuzhiyun status = "disabled"; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun gpio: gpio@40006000 { 39*4882a593Smuzhiyun compatible = "energymicro,efm32-gpio"; 40*4882a593Smuzhiyun reg = <0x40006000 0x1000>; 41*4882a593Smuzhiyun interrupts = <1 11>; 42*4882a593Smuzhiyun gpio-controller; 43*4882a593Smuzhiyun #gpio-cells = <2>; 44*4882a593Smuzhiyun interrupt-controller; 45*4882a593Smuzhiyun #interrupt-cells = <1>; 46*4882a593Smuzhiyun clocks = <&cmu clk_HFPERCLKGPIO>; 47*4882a593Smuzhiyun status = "ok"; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun i2c0: i2c@4000a000 { 51*4882a593Smuzhiyun #address-cells = <1>; 52*4882a593Smuzhiyun #size-cells = <0>; 53*4882a593Smuzhiyun compatible = "energymicro,efm32-i2c"; 54*4882a593Smuzhiyun reg = <0x4000a000 0x400>; 55*4882a593Smuzhiyun interrupts = <9>; 56*4882a593Smuzhiyun clocks = <&cmu clk_HFPERCLKI2C0>; 57*4882a593Smuzhiyun clock-frequency = <100000>; 58*4882a593Smuzhiyun status = "disabled"; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun i2c1: i2c@4000a400 { 62*4882a593Smuzhiyun #address-cells = <1>; 63*4882a593Smuzhiyun #size-cells = <0>; 64*4882a593Smuzhiyun compatible = "energymicro,efm32-i2c"; 65*4882a593Smuzhiyun reg = <0x4000a400 0x400>; 66*4882a593Smuzhiyun interrupts = <10>; 67*4882a593Smuzhiyun clocks = <&cmu clk_HFPERCLKI2C1>; 68*4882a593Smuzhiyun clock-frequency = <100000>; 69*4882a593Smuzhiyun status = "disabled"; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun spi0: spi@4000c000 { /* USART0 */ 73*4882a593Smuzhiyun #address-cells = <1>; 74*4882a593Smuzhiyun #size-cells = <0>; 75*4882a593Smuzhiyun compatible = "energymicro,efm32-spi"; 76*4882a593Smuzhiyun reg = <0x4000c000 0x400>; 77*4882a593Smuzhiyun interrupts = <3 4>; 78*4882a593Smuzhiyun clocks = <&cmu clk_HFPERCLKUSART0>; 79*4882a593Smuzhiyun status = "disabled"; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun spi1: spi@4000c400 { /* USART1 */ 83*4882a593Smuzhiyun #address-cells = <1>; 84*4882a593Smuzhiyun #size-cells = <0>; 85*4882a593Smuzhiyun compatible = "energymicro,efm32-spi"; 86*4882a593Smuzhiyun reg = <0x4000c400 0x400>; 87*4882a593Smuzhiyun interrupts = <15 16>; 88*4882a593Smuzhiyun clocks = <&cmu clk_HFPERCLKUSART1>; 89*4882a593Smuzhiyun status = "disabled"; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun spi2: spi@4000c800 { /* USART2 */ 93*4882a593Smuzhiyun #address-cells = <1>; 94*4882a593Smuzhiyun #size-cells = <0>; 95*4882a593Smuzhiyun compatible = "energymicro,efm32-spi"; 96*4882a593Smuzhiyun reg = <0x4000c800 0x400>; 97*4882a593Smuzhiyun interrupts = <18 19>; 98*4882a593Smuzhiyun clocks = <&cmu clk_HFPERCLKUSART2>; 99*4882a593Smuzhiyun status = "disabled"; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun uart0: uart@4000c000 { /* USART0 */ 103*4882a593Smuzhiyun compatible = "energymicro,efm32-uart"; 104*4882a593Smuzhiyun reg = <0x4000c000 0x400>; 105*4882a593Smuzhiyun interrupts = <3 4>; 106*4882a593Smuzhiyun clocks = <&cmu clk_HFPERCLKUSART0>; 107*4882a593Smuzhiyun status = "disabled"; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun uart1: uart@4000c400 { /* USART1 */ 111*4882a593Smuzhiyun compatible = "energymicro,efm32-uart"; 112*4882a593Smuzhiyun reg = <0x4000c400 0x400>; 113*4882a593Smuzhiyun interrupts = <15 16>; 114*4882a593Smuzhiyun clocks = <&cmu clk_HFPERCLKUSART1>; 115*4882a593Smuzhiyun status = "disabled"; 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun uart2: uart@4000c800 { /* USART2 */ 119*4882a593Smuzhiyun compatible = "energymicro,efm32-uart"; 120*4882a593Smuzhiyun reg = <0x4000c800 0x400>; 121*4882a593Smuzhiyun interrupts = <18 19>; 122*4882a593Smuzhiyun clocks = <&cmu clk_HFPERCLKUSART2>; 123*4882a593Smuzhiyun status = "disabled"; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun uart3: uart@4000e000 { /* UART0 */ 127*4882a593Smuzhiyun compatible = "energymicro,efm32-uart"; 128*4882a593Smuzhiyun reg = <0x4000e000 0x400>; 129*4882a593Smuzhiyun interrupts = <20 21>; 130*4882a593Smuzhiyun clocks = <&cmu clk_HFPERCLKUART0>; 131*4882a593Smuzhiyun status = "disabled"; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun uart4: uart@4000e400 { /* UART1 */ 135*4882a593Smuzhiyun compatible = "energymicro,efm32-uart"; 136*4882a593Smuzhiyun reg = <0x4000e400 0x400>; 137*4882a593Smuzhiyun interrupts = <22 23>; 138*4882a593Smuzhiyun clocks = <&cmu clk_HFPERCLKUART1>; 139*4882a593Smuzhiyun status = "disabled"; 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun timer0: timer@40010000 { 143*4882a593Smuzhiyun compatible = "energymicro,efm32-timer"; 144*4882a593Smuzhiyun reg = <0x40010000 0x400>; 145*4882a593Smuzhiyun interrupts = <2>; 146*4882a593Smuzhiyun clocks = <&cmu clk_HFPERCLKTIMER0>; 147*4882a593Smuzhiyun }; 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun timer1: timer@40010400 { 150*4882a593Smuzhiyun compatible = "energymicro,efm32-timer"; 151*4882a593Smuzhiyun reg = <0x40010400 0x400>; 152*4882a593Smuzhiyun interrupts = <12>; 153*4882a593Smuzhiyun clocks = <&cmu clk_HFPERCLKTIMER1>; 154*4882a593Smuzhiyun }; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun timer2: timer@40010800 { 157*4882a593Smuzhiyun compatible = "energymicro,efm32-timer"; 158*4882a593Smuzhiyun reg = <0x40010800 0x400>; 159*4882a593Smuzhiyun interrupts = <13>; 160*4882a593Smuzhiyun clocks = <&cmu clk_HFPERCLKTIMER2>; 161*4882a593Smuzhiyun }; 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun timer3: timer@40010c00 { 164*4882a593Smuzhiyun compatible = "energymicro,efm32-timer"; 165*4882a593Smuzhiyun reg = <0x40010c00 0x400>; 166*4882a593Smuzhiyun interrupts = <14>; 167*4882a593Smuzhiyun clocks = <&cmu clk_HFPERCLKTIMER3>; 168*4882a593Smuzhiyun }; 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun cmu: cmu@400c8000 { 171*4882a593Smuzhiyun compatible = "efm32gg,cmu"; 172*4882a593Smuzhiyun reg = <0x400c8000 0x400>; 173*4882a593Smuzhiyun interrupts = <32>; 174*4882a593Smuzhiyun #clock-cells = <1>; 175*4882a593Smuzhiyun }; 176*4882a593Smuzhiyun }; 177*4882a593Smuzhiyun}; 178