xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/ecx-common.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright 2011-2012 Calxeda, Inc.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun/ {
7*4882a593Smuzhiyun	chosen {
8*4882a593Smuzhiyun		bootargs = "console=ttyAMA0";
9*4882a593Smuzhiyun	};
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun	psci {
12*4882a593Smuzhiyun		compatible	= "arm,psci";
13*4882a593Smuzhiyun		method		= "smc";
14*4882a593Smuzhiyun		cpu_suspend	= <0x84000002>;
15*4882a593Smuzhiyun		cpu_off		= <0x84000004>;
16*4882a593Smuzhiyun		cpu_on		= <0x84000006>;
17*4882a593Smuzhiyun	};
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun	soc {
20*4882a593Smuzhiyun		#address-cells = <1>;
21*4882a593Smuzhiyun		#size-cells = <1>;
22*4882a593Smuzhiyun		compatible = "simple-bus";
23*4882a593Smuzhiyun		interrupt-parent = <&intc>;
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun		sata@ffe08000 {
26*4882a593Smuzhiyun			compatible = "calxeda,hb-ahci";
27*4882a593Smuzhiyun			reg = <0xffe08000 0x10000>;
28*4882a593Smuzhiyun			interrupts = <0 83 4>;
29*4882a593Smuzhiyun			dma-coherent;
30*4882a593Smuzhiyun			calxeda,port-phys = < &combophy5 0>, <&combophy0 0>,
31*4882a593Smuzhiyun					     <&combophy0 1>, <&combophy0 2>,
32*4882a593Smuzhiyun					     <&combophy0 3>;
33*4882a593Smuzhiyun			calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>,
34*4882a593Smuzhiyun					    <&gpioh 7 1>;
35*4882a593Smuzhiyun			calxeda,led-order = <4 0 1 2 3>;
36*4882a593Smuzhiyun		};
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun		sdhci@ffe0e000 {
39*4882a593Smuzhiyun			compatible = "calxeda,hb-sdhci";
40*4882a593Smuzhiyun			reg = <0xffe0e000 0x1000>;
41*4882a593Smuzhiyun			interrupts = <0 90 4>;
42*4882a593Smuzhiyun			clocks = <&eclk>;
43*4882a593Smuzhiyun			status = "disabled";
44*4882a593Smuzhiyun		};
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun		ipc@fff20000 {
47*4882a593Smuzhiyun			compatible = "arm,pl320", "arm,primecell";
48*4882a593Smuzhiyun			reg = <0xfff20000 0x1000>;
49*4882a593Smuzhiyun			interrupts = <0 7 4>;
50*4882a593Smuzhiyun			clocks = <&pclk>;
51*4882a593Smuzhiyun			clock-names = "apb_pclk";
52*4882a593Smuzhiyun		};
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun		gpioe: gpio@fff30000 {
55*4882a593Smuzhiyun			#gpio-cells = <2>;
56*4882a593Smuzhiyun			compatible = "arm,pl061", "arm,primecell";
57*4882a593Smuzhiyun			gpio-controller;
58*4882a593Smuzhiyun			reg = <0xfff30000 0x1000>;
59*4882a593Smuzhiyun			interrupts = <0 14 4>;
60*4882a593Smuzhiyun			clocks = <&pclk>;
61*4882a593Smuzhiyun			clock-names = "apb_pclk";
62*4882a593Smuzhiyun			status = "disabled";
63*4882a593Smuzhiyun		};
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun		gpiof: gpio@fff31000 {
66*4882a593Smuzhiyun			#gpio-cells = <2>;
67*4882a593Smuzhiyun			compatible = "arm,pl061", "arm,primecell";
68*4882a593Smuzhiyun			gpio-controller;
69*4882a593Smuzhiyun			reg = <0xfff31000 0x1000>;
70*4882a593Smuzhiyun			interrupts = <0 15 4>;
71*4882a593Smuzhiyun			clocks = <&pclk>;
72*4882a593Smuzhiyun			clock-names = "apb_pclk";
73*4882a593Smuzhiyun			status = "disabled";
74*4882a593Smuzhiyun		};
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun		gpiog: gpio@fff32000 {
77*4882a593Smuzhiyun			#gpio-cells = <2>;
78*4882a593Smuzhiyun			compatible = "arm,pl061", "arm,primecell";
79*4882a593Smuzhiyun			gpio-controller;
80*4882a593Smuzhiyun			reg = <0xfff32000 0x1000>;
81*4882a593Smuzhiyun			interrupts = <0 16 4>;
82*4882a593Smuzhiyun			clocks = <&pclk>;
83*4882a593Smuzhiyun			clock-names = "apb_pclk";
84*4882a593Smuzhiyun			status = "disabled";
85*4882a593Smuzhiyun		};
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun		gpioh: gpio@fff33000 {
88*4882a593Smuzhiyun			#gpio-cells = <2>;
89*4882a593Smuzhiyun			compatible = "arm,pl061", "arm,primecell";
90*4882a593Smuzhiyun			gpio-controller;
91*4882a593Smuzhiyun			reg = <0xfff33000 0x1000>;
92*4882a593Smuzhiyun			interrupts = <0 17 4>;
93*4882a593Smuzhiyun			clocks = <&pclk>;
94*4882a593Smuzhiyun			clock-names = "apb_pclk";
95*4882a593Smuzhiyun			status = "disabled";
96*4882a593Smuzhiyun		};
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun		timer@fff34000 {
99*4882a593Smuzhiyun			compatible = "arm,sp804", "arm,primecell";
100*4882a593Smuzhiyun			reg = <0xfff34000 0x1000>;
101*4882a593Smuzhiyun			interrupts = <0 18 4>;
102*4882a593Smuzhiyun			clocks = <&pclk>;
103*4882a593Smuzhiyun			clock-names = "apb_pclk";
104*4882a593Smuzhiyun		};
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun		rtc@fff35000 {
107*4882a593Smuzhiyun			compatible = "arm,pl031", "arm,primecell";
108*4882a593Smuzhiyun			reg = <0xfff35000 0x1000>;
109*4882a593Smuzhiyun			interrupts = <0 19 4>;
110*4882a593Smuzhiyun			clocks = <&pclk>;
111*4882a593Smuzhiyun			clock-names = "apb_pclk";
112*4882a593Smuzhiyun		};
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun		serial@fff36000 {
115*4882a593Smuzhiyun			compatible = "arm,pl011", "arm,primecell";
116*4882a593Smuzhiyun			reg = <0xfff36000 0x1000>;
117*4882a593Smuzhiyun			interrupts = <0 20 4>;
118*4882a593Smuzhiyun			clocks = <&pclk>, <&pclk>;
119*4882a593Smuzhiyun			clock-names = "uartclk", "apb_pclk";
120*4882a593Smuzhiyun		};
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun		smic@fff3a000 {
123*4882a593Smuzhiyun			compatible = "ipmi-smic";
124*4882a593Smuzhiyun			device_type = "ipmi";
125*4882a593Smuzhiyun			reg = <0xfff3a000 0x1000>;
126*4882a593Smuzhiyun			interrupts = <0 24 4>;
127*4882a593Smuzhiyun			reg-size = <4>;
128*4882a593Smuzhiyun			reg-spacing = <4>;
129*4882a593Smuzhiyun		};
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun		sregs@fff3c000 {
132*4882a593Smuzhiyun			compatible = "calxeda,hb-sregs";
133*4882a593Smuzhiyun			reg = <0xfff3c000 0x1000>;
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun			clocks {
136*4882a593Smuzhiyun				#address-cells = <1>;
137*4882a593Smuzhiyun				#size-cells = <0>;
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun				osc: oscillator {
140*4882a593Smuzhiyun					#clock-cells = <0>;
141*4882a593Smuzhiyun					compatible = "fixed-clock";
142*4882a593Smuzhiyun					clock-frequency = <33333000>;
143*4882a593Smuzhiyun				};
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun				ddrpll: ddrpll {
146*4882a593Smuzhiyun					#clock-cells = <0>;
147*4882a593Smuzhiyun					compatible = "calxeda,hb-pll-clock";
148*4882a593Smuzhiyun					clocks = <&osc>;
149*4882a593Smuzhiyun					reg = <0x108>;
150*4882a593Smuzhiyun				};
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun				a9pll: a9pll {
153*4882a593Smuzhiyun					#clock-cells = <0>;
154*4882a593Smuzhiyun					compatible = "calxeda,hb-pll-clock";
155*4882a593Smuzhiyun					clocks = <&osc>;
156*4882a593Smuzhiyun					reg = <0x100>;
157*4882a593Smuzhiyun				};
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun				a9periphclk: a9periphclk {
160*4882a593Smuzhiyun					#clock-cells = <0>;
161*4882a593Smuzhiyun					compatible = "calxeda,hb-a9periph-clock";
162*4882a593Smuzhiyun					clocks = <&a9pll>;
163*4882a593Smuzhiyun					reg = <0x104>;
164*4882a593Smuzhiyun				};
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun				a9bclk: a9bclk {
167*4882a593Smuzhiyun					#clock-cells = <0>;
168*4882a593Smuzhiyun					compatible = "calxeda,hb-a9bus-clock";
169*4882a593Smuzhiyun					clocks = <&a9pll>;
170*4882a593Smuzhiyun					reg = <0x104>;
171*4882a593Smuzhiyun				};
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun				emmcpll: emmcpll {
174*4882a593Smuzhiyun					#clock-cells = <0>;
175*4882a593Smuzhiyun					compatible = "calxeda,hb-pll-clock";
176*4882a593Smuzhiyun					clocks = <&osc>;
177*4882a593Smuzhiyun					reg = <0x10C>;
178*4882a593Smuzhiyun				};
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun				eclk: eclk {
181*4882a593Smuzhiyun					#clock-cells = <0>;
182*4882a593Smuzhiyun					compatible = "calxeda,hb-emmc-clock";
183*4882a593Smuzhiyun					clocks = <&emmcpll>;
184*4882a593Smuzhiyun					reg = <0x114>;
185*4882a593Smuzhiyun				};
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun				pclk: pclk {
188*4882a593Smuzhiyun					#clock-cells = <0>;
189*4882a593Smuzhiyun					compatible = "fixed-clock";
190*4882a593Smuzhiyun					clock-frequency = <150000000>;
191*4882a593Smuzhiyun				};
192*4882a593Smuzhiyun			};
193*4882a593Smuzhiyun		};
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun		dma@fff3d000 {
196*4882a593Smuzhiyun			compatible = "arm,pl330", "arm,primecell";
197*4882a593Smuzhiyun			reg = <0xfff3d000 0x1000>;
198*4882a593Smuzhiyun			interrupts = <0 92 4>;
199*4882a593Smuzhiyun			clocks = <&pclk>;
200*4882a593Smuzhiyun			clock-names = "apb_pclk";
201*4882a593Smuzhiyun		};
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun		ethernet@fff50000 {
204*4882a593Smuzhiyun			compatible = "calxeda,hb-xgmac";
205*4882a593Smuzhiyun			reg = <0xfff50000 0x1000>;
206*4882a593Smuzhiyun			interrupts = <0 77 4>, <0 78 4>, <0 79 4>;
207*4882a593Smuzhiyun			dma-coherent;
208*4882a593Smuzhiyun		};
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun		ethernet@fff51000 {
211*4882a593Smuzhiyun			compatible = "calxeda,hb-xgmac";
212*4882a593Smuzhiyun			reg = <0xfff51000 0x1000>;
213*4882a593Smuzhiyun			interrupts = <0 80 4>, <0 81 4>, <0 82 4>;
214*4882a593Smuzhiyun			dma-coherent;
215*4882a593Smuzhiyun		};
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun		combophy0: combo-phy@fff58000 {
218*4882a593Smuzhiyun			compatible = "calxeda,hb-combophy";
219*4882a593Smuzhiyun			#phy-cells = <1>;
220*4882a593Smuzhiyun			reg = <0xfff58000 0x1000>;
221*4882a593Smuzhiyun			phydev = <5>;
222*4882a593Smuzhiyun		};
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun		combophy5: combo-phy@fff5d000 {
225*4882a593Smuzhiyun			compatible = "calxeda,hb-combophy";
226*4882a593Smuzhiyun			#phy-cells = <1>;
227*4882a593Smuzhiyun			reg = <0xfff5d000 0x1000>;
228*4882a593Smuzhiyun			phydev = <31>;
229*4882a593Smuzhiyun		};
230*4882a593Smuzhiyun	};
231*4882a593Smuzhiyun};
232