1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/ 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Based on "omap4.dtsi" 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include "dra7.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun compatible = "ti,dra722", "ti,dra72", "ti,dra7"; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun aliases { 14*4882a593Smuzhiyun rproc0 = &ipu1; 15*4882a593Smuzhiyun rproc1 = &ipu2; 16*4882a593Smuzhiyun rproc2 = &dsp1; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun pmu { 20*4882a593Smuzhiyun compatible = "arm,cortex-a15-pmu"; 21*4882a593Smuzhiyun interrupt-parent = <&wakeupgen>; 22*4882a593Smuzhiyun interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun}; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun&l4_per2 { 27*4882a593Smuzhiyun target-module@5b000 { /* 0x4845b000, ap 59 46.0 */ 28*4882a593Smuzhiyun compatible = "ti,sysc-omap4", "ti,sysc"; 29*4882a593Smuzhiyun reg = <0x5b000 0x4>, 30*4882a593Smuzhiyun <0x5b010 0x4>; 31*4882a593Smuzhiyun reg-names = "rev", "sysc"; 32*4882a593Smuzhiyun ti,sysc-midle = <SYSC_IDLE_FORCE>, 33*4882a593Smuzhiyun <SYSC_IDLE_NO>; 34*4882a593Smuzhiyun ti,sysc-sidle = <SYSC_IDLE_FORCE>, 35*4882a593Smuzhiyun <SYSC_IDLE_NO>; 36*4882a593Smuzhiyun clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>; 37*4882a593Smuzhiyun clock-names = "fck"; 38*4882a593Smuzhiyun #address-cells = <1>; 39*4882a593Smuzhiyun #size-cells = <1>; 40*4882a593Smuzhiyun ranges = <0x0 0x5b000 0x1000>; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun cal: cal@0 { 43*4882a593Smuzhiyun compatible = "ti,dra72-cal"; 44*4882a593Smuzhiyun reg = <0x0000 0x400>, 45*4882a593Smuzhiyun <0x0800 0x40>, 46*4882a593Smuzhiyun <0x0900 0x40>; 47*4882a593Smuzhiyun reg-names = "cal_top", 48*4882a593Smuzhiyun "cal_rx_core0", 49*4882a593Smuzhiyun "cal_rx_core1"; 50*4882a593Smuzhiyun interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 51*4882a593Smuzhiyun ti,camerrx-control = <&scm_conf 0xE94>; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun ports { 54*4882a593Smuzhiyun #address-cells = <1>; 55*4882a593Smuzhiyun #size-cells = <0>; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun csi2_0: port@0 { 58*4882a593Smuzhiyun reg = <0>; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun csi2_1: port@1 { 61*4882a593Smuzhiyun reg = <1>; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun}; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun&dss { 69*4882a593Smuzhiyun reg = <0 0x80>, 70*4882a593Smuzhiyun <0x4054 0x4>, 71*4882a593Smuzhiyun <0x4300 0x20>; 72*4882a593Smuzhiyun reg-names = "dss", "pll1_clkctrl", "pll1"; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>, 75*4882a593Smuzhiyun <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 12>; 76*4882a593Smuzhiyun clock-names = "fck", "video1_clk"; 77*4882a593Smuzhiyun}; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun&mailbox5 { 80*4882a593Smuzhiyun mbox_ipu1_ipc3x: mbox-ipu1-ipc3x { 81*4882a593Smuzhiyun ti,mbox-tx = <6 2 2>; 82*4882a593Smuzhiyun ti,mbox-rx = <4 2 2>; 83*4882a593Smuzhiyun status = "disabled"; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun mbox_dsp1_ipc3x: mbox-dsp1-ipc3x { 86*4882a593Smuzhiyun ti,mbox-tx = <5 2 2>; 87*4882a593Smuzhiyun ti,mbox-rx = <1 2 2>; 88*4882a593Smuzhiyun status = "disabled"; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun}; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun&mailbox6 { 93*4882a593Smuzhiyun mbox_ipu2_ipc3x: mbox-ipu2-ipc3x { 94*4882a593Smuzhiyun ti,mbox-tx = <6 2 2>; 95*4882a593Smuzhiyun ti,mbox-rx = <4 2 2>; 96*4882a593Smuzhiyun status = "disabled"; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun}; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun&pcie1_rc { 101*4882a593Smuzhiyun compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie"; 102*4882a593Smuzhiyun}; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun&pcie1_ep { 105*4882a593Smuzhiyun compatible = "ti,dra726-pcie-ep", "ti,dra7-pcie-ep"; 106*4882a593Smuzhiyun}; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun&pcie2_rc { 109*4882a593Smuzhiyun compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie"; 110*4882a593Smuzhiyun}; 111