1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * MMC IOdelay values for TI's DRA7xx SoCs. 4*4882a593Smuzhiyun * Copyright (C) 2018 Texas Instruments 5*4882a593Smuzhiyun * Author: Kishon Vijay Abraham I <kishon@ti.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun&dra7_pmx_core { 9*4882a593Smuzhiyun mmc1_pins_default_no_clk_pu: mmc1_pins_default_no_clk_pu { 10*4882a593Smuzhiyun pinctrl-single,pins = < 11*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mmc1_clk.clk */ 12*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 13*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 14*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ 15*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ 16*4882a593Smuzhiyun DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ 17*4882a593Smuzhiyun >; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun}; 20