1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun#include "dm814x-clocks.dtsi" 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun/* Compared to dm814x, dra62x does not have hdic, l3 or dss PLLs */ 6*4882a593Smuzhiyun&adpll_hdvic_ck { 7*4882a593Smuzhiyun status = "disabled"; 8*4882a593Smuzhiyun}; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun&adpll_l3_ck { 11*4882a593Smuzhiyun status = "disabled"; 12*4882a593Smuzhiyun}; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun&adpll_dss_ck { 15*4882a593Smuzhiyun status = "disabled"; 16*4882a593Smuzhiyun}; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun/* Compared to dm814x, dra62x has interconnect clocks on isp PLL */ 19*4882a593Smuzhiyun&sysclk4_ck { 20*4882a593Smuzhiyun clocks = <&adpll_isp_ck 1>; 21*4882a593Smuzhiyun}; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun&sysclk5_ck { 24*4882a593Smuzhiyun clocks = <&adpll_isp_ck 1>; 25*4882a593Smuzhiyun}; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun&sysclk6_ck { 28*4882a593Smuzhiyun clocks = <&adpll_isp_ck 1>; 29*4882a593Smuzhiyun}; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun/* 32*4882a593Smuzhiyun * Compared to dm814x, dra62x has different shifts and more mux options. 33*4882a593Smuzhiyun * Please add the extra options for ysclk_14 and 16 if really needed. 34*4882a593Smuzhiyun */ 35*4882a593Smuzhiyun&timer1_fck { 36*4882a593Smuzhiyun clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck 37*4882a593Smuzhiyun &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; 38*4882a593Smuzhiyun ti,bit-shift = <4>; 39*4882a593Smuzhiyun}; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun&timer2_fck { 42*4882a593Smuzhiyun clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck 43*4882a593Smuzhiyun &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>; 44*4882a593Smuzhiyun ti,bit-shift = <8>; 45*4882a593Smuzhiyun}; 46