1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/dts-v1/; 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun#include "dove.dtsi" 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/ { 7*4882a593Smuzhiyun model = "SolidRun CuBox"; 8*4882a593Smuzhiyun compatible = "solidrun,cubox", "marvell,dove"; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun memory { 11*4882a593Smuzhiyun device_type = "memory"; 12*4882a593Smuzhiyun reg = <0x00000000 0x40000000>; 13*4882a593Smuzhiyun }; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun chosen { 16*4882a593Smuzhiyun bootargs = "console=ttyS0,115200n8 earlyprintk"; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun leds { 20*4882a593Smuzhiyun compatible = "gpio-leds"; 21*4882a593Smuzhiyun pinctrl-0 = <&pmx_gpio_18>; 22*4882a593Smuzhiyun pinctrl-names = "default"; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun power { 25*4882a593Smuzhiyun label = "Power"; 26*4882a593Smuzhiyun gpios = <&gpio0 18 1>; 27*4882a593Smuzhiyun default-state = "keep"; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun regulators { 32*4882a593Smuzhiyun compatible = "simple-bus"; 33*4882a593Smuzhiyun #address-cells = <1>; 34*4882a593Smuzhiyun #size-cells = <0>; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun usb_power: regulator@1 { 37*4882a593Smuzhiyun compatible = "regulator-fixed"; 38*4882a593Smuzhiyun reg = <1>; 39*4882a593Smuzhiyun regulator-name = "USB Power"; 40*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 41*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 42*4882a593Smuzhiyun enable-active-high; 43*4882a593Smuzhiyun regulator-always-on; 44*4882a593Smuzhiyun regulator-boot-on; 45*4882a593Smuzhiyun gpio = <&gpio0 1 0>; 46*4882a593Smuzhiyun pinctrl-0 = <&pmx_gpio_1>; 47*4882a593Smuzhiyun pinctrl-names = "default"; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun clocks { 52*4882a593Smuzhiyun /* 25MHz reference crystal */ 53*4882a593Smuzhiyun ref25: oscillator { 54*4882a593Smuzhiyun compatible = "fixed-clock"; 55*4882a593Smuzhiyun #clock-cells = <0>; 56*4882a593Smuzhiyun clock-frequency = <25000000>; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun ir_recv: ir-receiver { 61*4882a593Smuzhiyun compatible = "gpio-ir-receiver"; 62*4882a593Smuzhiyun gpios = <&gpio0 19 1>; 63*4882a593Smuzhiyun pinctrl-0 = <&pmx_gpio_19>; 64*4882a593Smuzhiyun pinctrl-names = "default"; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun gpu-subsystem { 68*4882a593Smuzhiyun status = "okay"; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun}; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun&uart0 { status = "okay"; }; 73*4882a593Smuzhiyun&sata0 { status = "okay"; }; 74*4882a593Smuzhiyun&mdio { status = "okay"; }; 75*4882a593Smuzhiyunð { status = "okay"; }; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyunðphy { 78*4882a593Smuzhiyun compatible = "marvell,88e1310"; 79*4882a593Smuzhiyun reg = <1>; 80*4882a593Smuzhiyun}; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun&gpu { 83*4882a593Smuzhiyun status = "okay"; 84*4882a593Smuzhiyun}; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun&i2c0 { 87*4882a593Smuzhiyun status = "okay"; 88*4882a593Smuzhiyun clock-frequency = <100000>; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun si5351: clock-generator@60 { 91*4882a593Smuzhiyun compatible = "silabs,si5351a-msop"; 92*4882a593Smuzhiyun reg = <0x60>; 93*4882a593Smuzhiyun #address-cells = <1>; 94*4882a593Smuzhiyun #size-cells = <0>; 95*4882a593Smuzhiyun #clock-cells = <1>; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* connect xtal input to 25MHz reference */ 98*4882a593Smuzhiyun clocks = <&ref25>; 99*4882a593Smuzhiyun clock-names = "xtal"; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun /* connect xtal input as source of pll0 and pll1 */ 102*4882a593Smuzhiyun silabs,pll-source = <0 0>, <1 0>; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun clkout0 { 105*4882a593Smuzhiyun reg = <0>; 106*4882a593Smuzhiyun silabs,drive-strength = <8>; 107*4882a593Smuzhiyun silabs,multisynth-source = <0>; 108*4882a593Smuzhiyun silabs,clock-source = <0>; 109*4882a593Smuzhiyun silabs,pll-master; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun clkout2 { 113*4882a593Smuzhiyun reg = <2>; 114*4882a593Smuzhiyun silabs,drive-strength = <8>; 115*4882a593Smuzhiyun silabs,multisynth-source = <1>; 116*4882a593Smuzhiyun silabs,clock-source = <0>; 117*4882a593Smuzhiyun silabs,pll-master; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun}; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun&sdio0 { 123*4882a593Smuzhiyun status = "okay"; 124*4882a593Smuzhiyun}; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun&spi0 { 127*4882a593Smuzhiyun status = "okay"; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun /* spi0.0: 4M Flash Winbond W25Q32BV */ 130*4882a593Smuzhiyun spi-flash@0 { 131*4882a593Smuzhiyun compatible = "st,w25q32"; 132*4882a593Smuzhiyun spi-max-frequency = <20000000>; 133*4882a593Smuzhiyun reg = <0>; 134*4882a593Smuzhiyun }; 135*4882a593Smuzhiyun}; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun&audio1 { 138*4882a593Smuzhiyun status = "okay"; 139*4882a593Smuzhiyun clocks = <&gate_clk 13>, <&si5351 2>; 140*4882a593Smuzhiyun clock-names = "internal", "extclk"; 141*4882a593Smuzhiyun pinctrl-0 = <&pmx_audio1_i2s1_spdifo &pmx_audio1_extclk>; 142*4882a593Smuzhiyun pinctrl-names = "default"; 143*4882a593Smuzhiyun}; 144