xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/dm816x.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public License
3*4882a593Smuzhiyun * version 2.  This program is licensed "as is" without any warranty of any
4*4882a593Smuzhiyun * kind, whether express or implied.
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun#include <dt-bindings/bus/ti-sysc.h>
8*4882a593Smuzhiyun#include <dt-bindings/clock/dm816.h>
9*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
10*4882a593Smuzhiyun#include <dt-bindings/pinctrl/omap.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun/ {
13*4882a593Smuzhiyun	compatible = "ti,dm816";
14*4882a593Smuzhiyun	interrupt-parent = <&intc>;
15*4882a593Smuzhiyun	#address-cells = <1>;
16*4882a593Smuzhiyun	#size-cells = <1>;
17*4882a593Smuzhiyun	chosen { };
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun	aliases {
20*4882a593Smuzhiyun		i2c0 = &i2c1;
21*4882a593Smuzhiyun		i2c1 = &i2c2;
22*4882a593Smuzhiyun		serial0 = &uart1;
23*4882a593Smuzhiyun		serial1 = &uart2;
24*4882a593Smuzhiyun		serial2 = &uart3;
25*4882a593Smuzhiyun		ethernet0 = &eth0;
26*4882a593Smuzhiyun		ethernet1 = &eth1;
27*4882a593Smuzhiyun	};
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun	cpus {
30*4882a593Smuzhiyun		#address-cells = <1>;
31*4882a593Smuzhiyun		#size-cells = <0>;
32*4882a593Smuzhiyun		cpu@0 {
33*4882a593Smuzhiyun			compatible = "arm,cortex-a8";
34*4882a593Smuzhiyun			device_type = "cpu";
35*4882a593Smuzhiyun			reg = <0>;
36*4882a593Smuzhiyun		};
37*4882a593Smuzhiyun	};
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun	pmu {
40*4882a593Smuzhiyun		compatible = "arm,cortex-a8-pmu";
41*4882a593Smuzhiyun		interrupts = <3>;
42*4882a593Smuzhiyun	};
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun	/*
45*4882a593Smuzhiyun	 * The soc node represents the soc top level view. It is used for IPs
46*4882a593Smuzhiyun	 * that are not memory mapped in the MPU view or for the MPU itself.
47*4882a593Smuzhiyun	 */
48*4882a593Smuzhiyun	soc {
49*4882a593Smuzhiyun		compatible = "ti,omap-infra";
50*4882a593Smuzhiyun		mpu {
51*4882a593Smuzhiyun			compatible = "ti,omap3-mpu";
52*4882a593Smuzhiyun			ti,hwmods = "mpu";
53*4882a593Smuzhiyun		};
54*4882a593Smuzhiyun	};
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun	/*
57*4882a593Smuzhiyun	 * XXX: Use a flat representation of the dm816x interconnect.
58*4882a593Smuzhiyun	 * The real dm816x interconnect network is quite complex. Since
59*4882a593Smuzhiyun	 * it will not bring real advantage to represent that in DT
60*4882a593Smuzhiyun	 * for the moment, just use a fake OCP bus entry to represent
61*4882a593Smuzhiyun	 * the whole bus hierarchy.
62*4882a593Smuzhiyun	 */
63*4882a593Smuzhiyun	ocp {
64*4882a593Smuzhiyun		compatible = "simple-bus";
65*4882a593Smuzhiyun		reg = <0x44000000 0x10000>;
66*4882a593Smuzhiyun		interrupts = <9 10>;
67*4882a593Smuzhiyun		#address-cells = <1>;
68*4882a593Smuzhiyun		#size-cells = <1>;
69*4882a593Smuzhiyun		ranges;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun		prcm: prcm@48180000 {
72*4882a593Smuzhiyun			compatible = "ti,dm816-prcm", "simple-bus";
73*4882a593Smuzhiyun			reg = <0x48180000 0x4000>;
74*4882a593Smuzhiyun			#address-cells = <1>;
75*4882a593Smuzhiyun			#size-cells = <1>;
76*4882a593Smuzhiyun			ranges = <0 0x48180000 0x4000>;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun			prcm_clocks: clocks {
79*4882a593Smuzhiyun				#address-cells = <1>;
80*4882a593Smuzhiyun				#size-cells = <0>;
81*4882a593Smuzhiyun			};
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun			prcm_clockdomains: clockdomains {
84*4882a593Smuzhiyun			};
85*4882a593Smuzhiyun		};
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun		scrm: scrm@48140000 {
88*4882a593Smuzhiyun			compatible = "ti,dm816-scrm", "simple-bus";
89*4882a593Smuzhiyun			reg = <0x48140000 0x21000>;
90*4882a593Smuzhiyun			#address-cells = <1>;
91*4882a593Smuzhiyun			#size-cells = <1>;
92*4882a593Smuzhiyun			#pinctrl-cells = <1>;
93*4882a593Smuzhiyun			ranges = <0 0x48140000 0x21000>;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun			dm816x_pinmux: pinmux@800 {
96*4882a593Smuzhiyun				compatible = "pinctrl-single";
97*4882a593Smuzhiyun				reg = <0x800 0x50a>;
98*4882a593Smuzhiyun				#address-cells = <1>;
99*4882a593Smuzhiyun				#size-cells = <0>;
100*4882a593Smuzhiyun				#pinctrl-cells = <1>;
101*4882a593Smuzhiyun				pinctrl-single,register-width = <16>;
102*4882a593Smuzhiyun				pinctrl-single,function-mask = <0xf>;
103*4882a593Smuzhiyun			};
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun			/* Device Configuration Registers */
106*4882a593Smuzhiyun			scm_conf: syscon@600 {
107*4882a593Smuzhiyun				compatible = "syscon", "simple-bus";
108*4882a593Smuzhiyun				reg = <0x600 0x110>;
109*4882a593Smuzhiyun				#address-cells = <1>;
110*4882a593Smuzhiyun				#size-cells = <1>;
111*4882a593Smuzhiyun				ranges = <0 0x600 0x110>;
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun				usb_phy0: usb-phy@20 {
114*4882a593Smuzhiyun					compatible = "ti,dm8168-usb-phy";
115*4882a593Smuzhiyun					reg = <0x20 0x8>;
116*4882a593Smuzhiyun					reg-names = "phy";
117*4882a593Smuzhiyun					clocks = <&main_fapll 6>;
118*4882a593Smuzhiyun					clock-names = "refclk";
119*4882a593Smuzhiyun					#phy-cells = <0>;
120*4882a593Smuzhiyun					syscon = <&scm_conf>;
121*4882a593Smuzhiyun				};
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun				usb_phy1: usb-phy@28 {
124*4882a593Smuzhiyun					compatible = "ti,dm8168-usb-phy";
125*4882a593Smuzhiyun					reg = <0x28 0x8>;
126*4882a593Smuzhiyun					reg-names = "phy";
127*4882a593Smuzhiyun					clocks = <&main_fapll 6>;
128*4882a593Smuzhiyun					clock-names = "refclk";
129*4882a593Smuzhiyun					#phy-cells = <0>;
130*4882a593Smuzhiyun					syscon = <&scm_conf>;
131*4882a593Smuzhiyun				};
132*4882a593Smuzhiyun			};
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun			scrm_clocks: clocks {
135*4882a593Smuzhiyun				#address-cells = <1>;
136*4882a593Smuzhiyun				#size-cells = <0>;
137*4882a593Smuzhiyun			};
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun			scrm_clockdomains: clockdomains {
140*4882a593Smuzhiyun			};
141*4882a593Smuzhiyun		};
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun		target-module@49000000 {
144*4882a593Smuzhiyun			compatible = "ti,sysc-omap4", "ti,sysc";
145*4882a593Smuzhiyun			reg = <0x49000000 0x4>;
146*4882a593Smuzhiyun			reg-names = "rev";
147*4882a593Smuzhiyun			clocks = <&alwon_clkctrl DM816_TPCC_CLKCTRL 0>;
148*4882a593Smuzhiyun			clock-names = "fck";
149*4882a593Smuzhiyun			#address-cells = <1>;
150*4882a593Smuzhiyun			#size-cells = <1>;
151*4882a593Smuzhiyun			ranges = <0x0 0x49000000 0x10000>;
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun			edma: dma@0 {
154*4882a593Smuzhiyun				compatible = "ti,edma3-tpcc";
155*4882a593Smuzhiyun				reg = <0 0x10000>;
156*4882a593Smuzhiyun				reg-names = "edma3_cc";
157*4882a593Smuzhiyun				interrupts = <12 13 14>;
158*4882a593Smuzhiyun				interrupt-names = "edma3_ccint", "edma3_mperr",
159*4882a593Smuzhiyun						  "edma3_ccerrint";
160*4882a593Smuzhiyun				dma-requests = <64>;
161*4882a593Smuzhiyun				#dma-cells = <2>;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun				ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
164*4882a593Smuzhiyun					   <&edma_tptc2 3>, <&edma_tptc3 0>;
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun				ti,edma-memcpy-channels = <20 21>;
167*4882a593Smuzhiyun			};
168*4882a593Smuzhiyun		};
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun		target-module@49800000 {
171*4882a593Smuzhiyun			compatible = "ti,sysc-omap4", "ti,sysc";
172*4882a593Smuzhiyun			reg = <0x49800000 0x4>,
173*4882a593Smuzhiyun			      <0x49800010 0x4>;
174*4882a593Smuzhiyun			reg-names = "rev", "sysc";
175*4882a593Smuzhiyun			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
176*4882a593Smuzhiyun			ti,sysc-midle = <SYSC_IDLE_FORCE>;
177*4882a593Smuzhiyun			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
178*4882a593Smuzhiyun					<SYSC_IDLE_SMART>;
179*4882a593Smuzhiyun			clocks = <&alwon_clkctrl DM816_TPTC0_CLKCTRL 0>;
180*4882a593Smuzhiyun			clock-names = "fck";
181*4882a593Smuzhiyun			#address-cells = <1>;
182*4882a593Smuzhiyun			#size-cells = <1>;
183*4882a593Smuzhiyun			ranges = <0x0 0x49800000 0x100000>;
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun			edma_tptc0: dma@0 {
186*4882a593Smuzhiyun				compatible = "ti,edma3-tptc";
187*4882a593Smuzhiyun				reg = <0 0x100000>;
188*4882a593Smuzhiyun				interrupts = <112>;
189*4882a593Smuzhiyun				interrupt-names = "edma3_tcerrint";
190*4882a593Smuzhiyun			};
191*4882a593Smuzhiyun		};
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun		target-module@49900000 {
194*4882a593Smuzhiyun			compatible = "ti,sysc-omap4", "ti,sysc";
195*4882a593Smuzhiyun			reg = <0x49900000 0x4>,
196*4882a593Smuzhiyun			      <0x49900010 0x4>;
197*4882a593Smuzhiyun			reg-names = "rev", "sysc";
198*4882a593Smuzhiyun			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
199*4882a593Smuzhiyun			ti,sysc-midle = <SYSC_IDLE_FORCE>;
200*4882a593Smuzhiyun			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
201*4882a593Smuzhiyun					<SYSC_IDLE_SMART>;
202*4882a593Smuzhiyun			clocks = <&alwon_clkctrl DM816_TPTC1_CLKCTRL 0>;
203*4882a593Smuzhiyun			clock-names = "fck";
204*4882a593Smuzhiyun			#address-cells = <1>;
205*4882a593Smuzhiyun			#size-cells = <1>;
206*4882a593Smuzhiyun			ranges = <0x0 0x49900000 0x100000>;
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun			edma_tptc1: dma@0 {
209*4882a593Smuzhiyun				compatible = "ti,edma3-tptc";
210*4882a593Smuzhiyun				reg = <0 0x100000>;
211*4882a593Smuzhiyun				interrupts = <113>;
212*4882a593Smuzhiyun				interrupt-names = "edma3_tcerrint";
213*4882a593Smuzhiyun			};
214*4882a593Smuzhiyun		};
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun		target-module@49a00000 {
217*4882a593Smuzhiyun			compatible = "ti,sysc-omap4", "ti,sysc";
218*4882a593Smuzhiyun			reg = <0x49a00000 0x4>,
219*4882a593Smuzhiyun			      <0x49a00010 0x4>;
220*4882a593Smuzhiyun			reg-names = "rev", "sysc";
221*4882a593Smuzhiyun			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
222*4882a593Smuzhiyun			ti,sysc-midle = <SYSC_IDLE_FORCE>;
223*4882a593Smuzhiyun			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
224*4882a593Smuzhiyun					<SYSC_IDLE_SMART>;
225*4882a593Smuzhiyun			clocks = <&alwon_clkctrl DM816_TPTC2_CLKCTRL 0>;
226*4882a593Smuzhiyun			clock-names = "fck";
227*4882a593Smuzhiyun			#address-cells = <1>;
228*4882a593Smuzhiyun			#size-cells = <1>;
229*4882a593Smuzhiyun			ranges = <0x0 0x49a00000 0x100000>;
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun			edma_tptc2: dma@0 {
232*4882a593Smuzhiyun				compatible = "ti,edma3-tptc";
233*4882a593Smuzhiyun				reg = <0 0x100000>;
234*4882a593Smuzhiyun				interrupts = <114>;
235*4882a593Smuzhiyun				interrupt-names = "edma3_tcerrint";
236*4882a593Smuzhiyun			};
237*4882a593Smuzhiyun		};
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun		target-module@49b00000 {
240*4882a593Smuzhiyun			compatible = "ti,sysc-omap4", "ti,sysc";
241*4882a593Smuzhiyun			reg = <0x49b00000 0x4>,
242*4882a593Smuzhiyun			      <0x49b00010 0x4>;
243*4882a593Smuzhiyun			reg-names = "rev", "sysc";
244*4882a593Smuzhiyun			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
245*4882a593Smuzhiyun			ti,sysc-midle = <SYSC_IDLE_FORCE>;
246*4882a593Smuzhiyun			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
247*4882a593Smuzhiyun					<SYSC_IDLE_SMART>;
248*4882a593Smuzhiyun			clocks = <&alwon_clkctrl DM816_TPTC3_CLKCTRL 0>;
249*4882a593Smuzhiyun			clock-names = "fck";
250*4882a593Smuzhiyun			#address-cells = <1>;
251*4882a593Smuzhiyun			#size-cells = <1>;
252*4882a593Smuzhiyun			ranges = <0x0 0x49b00000 0x100000>;
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun			edma_tptc3: dma@0 {
255*4882a593Smuzhiyun				compatible = "ti,edma3-tptc";
256*4882a593Smuzhiyun				reg = <0 0x100000>;
257*4882a593Smuzhiyun				interrupts = <115>;
258*4882a593Smuzhiyun				interrupt-names = "edma3_tcerrint";
259*4882a593Smuzhiyun			};
260*4882a593Smuzhiyun		};
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun		elm: elm@48080000 {
263*4882a593Smuzhiyun			compatible = "ti,am3352-elm";
264*4882a593Smuzhiyun			ti,hwmods = "elm";
265*4882a593Smuzhiyun			reg = <0x48080000 0x2000>;
266*4882a593Smuzhiyun			interrupts = <4>;
267*4882a593Smuzhiyun		};
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun		gpio1: gpio@48032000 {
270*4882a593Smuzhiyun			compatible = "ti,omap4-gpio";
271*4882a593Smuzhiyun			ti,hwmods = "gpio1";
272*4882a593Smuzhiyun			ti,gpio-always-on;
273*4882a593Smuzhiyun			reg = <0x48032000 0x1000>;
274*4882a593Smuzhiyun			interrupts = <96>;
275*4882a593Smuzhiyun			gpio-controller;
276*4882a593Smuzhiyun			#gpio-cells = <2>;
277*4882a593Smuzhiyun			interrupt-controller;
278*4882a593Smuzhiyun			#interrupt-cells = <2>;
279*4882a593Smuzhiyun		};
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun		gpio2: gpio@4804c000 {
282*4882a593Smuzhiyun			compatible = "ti,omap4-gpio";
283*4882a593Smuzhiyun			ti,hwmods = "gpio2";
284*4882a593Smuzhiyun			ti,gpio-always-on;
285*4882a593Smuzhiyun			reg = <0x4804c000 0x1000>;
286*4882a593Smuzhiyun			interrupts = <98>;
287*4882a593Smuzhiyun			gpio-controller;
288*4882a593Smuzhiyun			#gpio-cells = <2>;
289*4882a593Smuzhiyun			interrupt-controller;
290*4882a593Smuzhiyun			#interrupt-cells = <2>;
291*4882a593Smuzhiyun		};
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun		gpmc: gpmc@50000000 {
294*4882a593Smuzhiyun			compatible = "ti,am3352-gpmc";
295*4882a593Smuzhiyun			ti,hwmods = "gpmc";
296*4882a593Smuzhiyun			reg = <0x50000000 0x2000>;
297*4882a593Smuzhiyun			#address-cells = <2>;
298*4882a593Smuzhiyun			#size-cells = <1>;
299*4882a593Smuzhiyun			interrupts = <100>;
300*4882a593Smuzhiyun			dmas = <&edma 52 0>;
301*4882a593Smuzhiyun			dma-names = "rxtx";
302*4882a593Smuzhiyun			gpmc,num-cs = <6>;
303*4882a593Smuzhiyun			gpmc,num-waitpins = <2>;
304*4882a593Smuzhiyun			interrupt-controller;
305*4882a593Smuzhiyun			#interrupt-cells = <2>;
306*4882a593Smuzhiyun			gpio-controller;
307*4882a593Smuzhiyun			#gpio-cells = <2>;
308*4882a593Smuzhiyun		};
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun		i2c1: i2c@48028000 {
311*4882a593Smuzhiyun			compatible = "ti,omap4-i2c";
312*4882a593Smuzhiyun			ti,hwmods = "i2c1";
313*4882a593Smuzhiyun			reg = <0x48028000 0x1000>;
314*4882a593Smuzhiyun			#address-cells = <1>;
315*4882a593Smuzhiyun			#size-cells = <0>;
316*4882a593Smuzhiyun			interrupts = <70>;
317*4882a593Smuzhiyun			dmas = <&edma 58 0 &edma 59 0>;
318*4882a593Smuzhiyun			dma-names = "tx", "rx";
319*4882a593Smuzhiyun		};
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun		i2c2: i2c@4802a000 {
322*4882a593Smuzhiyun			compatible = "ti,omap4-i2c";
323*4882a593Smuzhiyun			ti,hwmods = "i2c2";
324*4882a593Smuzhiyun			reg = <0x4802a000 0x1000>;
325*4882a593Smuzhiyun			#address-cells = <1>;
326*4882a593Smuzhiyun			#size-cells = <0>;
327*4882a593Smuzhiyun			interrupts = <71>;
328*4882a593Smuzhiyun			dmas = <&edma 60 0 &edma 61 0>;
329*4882a593Smuzhiyun			dma-names = "tx", "rx";
330*4882a593Smuzhiyun		};
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun		intc: interrupt-controller@48200000 {
333*4882a593Smuzhiyun			compatible = "ti,dm816-intc";
334*4882a593Smuzhiyun			interrupt-controller;
335*4882a593Smuzhiyun			#interrupt-cells = <1>;
336*4882a593Smuzhiyun			reg = <0x48200000 0x1000>;
337*4882a593Smuzhiyun		};
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun		rtc: rtc@480c0000 {
340*4882a593Smuzhiyun			compatible = "ti,am3352-rtc", "ti,da830-rtc";
341*4882a593Smuzhiyun			reg = <0x480c0000 0x1000>;
342*4882a593Smuzhiyun			interrupts = <75 76>;
343*4882a593Smuzhiyun			ti,hwmods = "rtc";
344*4882a593Smuzhiyun		};
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun		mailbox: mailbox@480c8000 {
347*4882a593Smuzhiyun			compatible = "ti,omap4-mailbox";
348*4882a593Smuzhiyun			reg = <0x480c8000 0x2000>;
349*4882a593Smuzhiyun			interrupts = <77>;
350*4882a593Smuzhiyun			ti,hwmods = "mailbox";
351*4882a593Smuzhiyun			#mbox-cells = <1>;
352*4882a593Smuzhiyun			ti,mbox-num-users = <4>;
353*4882a593Smuzhiyun			ti,mbox-num-fifos = <12>;
354*4882a593Smuzhiyun			mbox_dsp: mbox-dsp {
355*4882a593Smuzhiyun				ti,mbox-tx = <3 0 0>;
356*4882a593Smuzhiyun				ti,mbox-rx = <0 0 0>;
357*4882a593Smuzhiyun			};
358*4882a593Smuzhiyun		};
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun		spinbox: spinbox@480ca000 {
361*4882a593Smuzhiyun			compatible = "ti,omap4-hwspinlock";
362*4882a593Smuzhiyun			reg = <0x480ca000 0x2000>;
363*4882a593Smuzhiyun			ti,hwmods = "spinbox";
364*4882a593Smuzhiyun			#hwlock-cells = <1>;
365*4882a593Smuzhiyun		};
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun		mdio: mdio@4a100800 {
368*4882a593Smuzhiyun			compatible = "ti,davinci_mdio";
369*4882a593Smuzhiyun			#address-cells = <1>;
370*4882a593Smuzhiyun			#size-cells = <0>;
371*4882a593Smuzhiyun			reg = <0x4a100800 0x100>;
372*4882a593Smuzhiyun			ti,hwmods = "davinci_mdio";
373*4882a593Smuzhiyun			bus_freq = <1000000>;
374*4882a593Smuzhiyun			phy0: ethernet-phy@0 {
375*4882a593Smuzhiyun				reg = <1>;
376*4882a593Smuzhiyun			};
377*4882a593Smuzhiyun			phy1: ethernet-phy@1 {
378*4882a593Smuzhiyun				reg = <2>;
379*4882a593Smuzhiyun			};
380*4882a593Smuzhiyun		};
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun		eth0: ethernet@4a100000 {
383*4882a593Smuzhiyun			compatible = "ti,dm816-emac";
384*4882a593Smuzhiyun			ti,hwmods = "emac0";
385*4882a593Smuzhiyun			reg = <0x4a100000 0x800
386*4882a593Smuzhiyun			       0x4a100900 0x3700>;
387*4882a593Smuzhiyun			clocks = <&sysclk24_ck>;
388*4882a593Smuzhiyun			syscon = <&scm_conf>;
389*4882a593Smuzhiyun			ti,davinci-ctrl-reg-offset = <0>;
390*4882a593Smuzhiyun			ti,davinci-ctrl-mod-reg-offset = <0x900>;
391*4882a593Smuzhiyun			ti,davinci-ctrl-ram-offset = <0x2000>;
392*4882a593Smuzhiyun			ti,davinci-ctrl-ram-size = <0x2000>;
393*4882a593Smuzhiyun			interrupts = <40 41 42 43>;
394*4882a593Smuzhiyun			phy-handle = <&phy0>;
395*4882a593Smuzhiyun		};
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun		eth1: ethernet@4a120000 {
398*4882a593Smuzhiyun			compatible = "ti,dm816-emac";
399*4882a593Smuzhiyun			ti,hwmods = "emac1";
400*4882a593Smuzhiyun			reg = <0x4a120000 0x4000>;
401*4882a593Smuzhiyun			clocks = <&sysclk24_ck>;
402*4882a593Smuzhiyun			syscon = <&scm_conf>;
403*4882a593Smuzhiyun			ti,davinci-ctrl-reg-offset = <0>;
404*4882a593Smuzhiyun			ti,davinci-ctrl-mod-reg-offset = <0x900>;
405*4882a593Smuzhiyun			ti,davinci-ctrl-ram-offset = <0x2000>;
406*4882a593Smuzhiyun			ti,davinci-ctrl-ram-size = <0x2000>;
407*4882a593Smuzhiyun			interrupts = <44 45 46 47>;
408*4882a593Smuzhiyun			phy-handle = <&phy1>;
409*4882a593Smuzhiyun		};
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun		sata: sata@4a140000 {
412*4882a593Smuzhiyun			compatible = "ti,dm816-ahci";
413*4882a593Smuzhiyun			reg = <0x4a140000 0x10000>;
414*4882a593Smuzhiyun			interrupts = <16>;
415*4882a593Smuzhiyun			ti,hwmods = "sata";
416*4882a593Smuzhiyun		};
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun		mcspi1: spi@48030000 {
419*4882a593Smuzhiyun			compatible = "ti,omap4-mcspi";
420*4882a593Smuzhiyun			reg = <0x48030000 0x1000>;
421*4882a593Smuzhiyun			#address-cells = <1>;
422*4882a593Smuzhiyun			#size-cells = <0>;
423*4882a593Smuzhiyun			interrupts = <65>;
424*4882a593Smuzhiyun			ti,spi-num-cs = <4>;
425*4882a593Smuzhiyun			ti,hwmods = "mcspi1";
426*4882a593Smuzhiyun			dmas = <&edma 16 0 &edma 17 0
427*4882a593Smuzhiyun				&edma 18 0 &edma 19 0
428*4882a593Smuzhiyun				&edma 20 0 &edma 21 0
429*4882a593Smuzhiyun				&edma 22 0 &edma 23 0>;
430*4882a593Smuzhiyun			dma-names = "tx0", "rx0", "tx1", "rx1",
431*4882a593Smuzhiyun				    "tx2", "rx2", "tx3", "rx3";
432*4882a593Smuzhiyun		};
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun		mmc1: mmc@48060000 {
435*4882a593Smuzhiyun			compatible = "ti,omap4-hsmmc";
436*4882a593Smuzhiyun			reg = <0x48060000 0x11000>;
437*4882a593Smuzhiyun			ti,hwmods = "mmc1";
438*4882a593Smuzhiyun			interrupts = <64>;
439*4882a593Smuzhiyun			dmas = <&edma 24 0 &edma 25 0>;
440*4882a593Smuzhiyun			dma-names = "tx", "rx";
441*4882a593Smuzhiyun		};
442*4882a593Smuzhiyun
443*4882a593Smuzhiyun		timer1_target: target-module@4802e000 {
444*4882a593Smuzhiyun			compatible = "ti,sysc-omap4-timer", "ti,sysc";
445*4882a593Smuzhiyun			reg = <0x4802e000 0x4>,
446*4882a593Smuzhiyun			      <0x4802e010 0x4>;
447*4882a593Smuzhiyun			reg-names = "rev", "sysc";
448*4882a593Smuzhiyun			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
449*4882a593Smuzhiyun			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
450*4882a593Smuzhiyun					<SYSC_IDLE_NO>,
451*4882a593Smuzhiyun					<SYSC_IDLE_SMART>,
452*4882a593Smuzhiyun					<SYSC_IDLE_SMART_WKUP>;
453*4882a593Smuzhiyun			clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>;
454*4882a593Smuzhiyun			clock-names = "fck";
455*4882a593Smuzhiyun			#address-cells = <1>;
456*4882a593Smuzhiyun			#size-cells = <1>;
457*4882a593Smuzhiyun			ranges = <0x0 0x4802e000 0x1000>;
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun			timer1: timer@0 {
460*4882a593Smuzhiyun				compatible = "ti,dm816-timer";
461*4882a593Smuzhiyun				reg = <0 0x1000>;
462*4882a593Smuzhiyun				interrupts = <67>;
463*4882a593Smuzhiyun				ti,timer-alwon;
464*4882a593Smuzhiyun				clocks = <&alwon_clkctrl DM816_TIMER1_CLKCTRL 0>;
465*4882a593Smuzhiyun				clock-names = "fck";
466*4882a593Smuzhiyun			};
467*4882a593Smuzhiyun		};
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun		timer2_target: target-module@48040000 {
470*4882a593Smuzhiyun			compatible = "ti,sysc-omap4-timer", "ti,sysc";
471*4882a593Smuzhiyun			reg = <0x48040000 0x4>,
472*4882a593Smuzhiyun			      <0x48040010 0x4>;
473*4882a593Smuzhiyun			reg-names = "rev", "sysc";
474*4882a593Smuzhiyun			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
475*4882a593Smuzhiyun			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
476*4882a593Smuzhiyun					<SYSC_IDLE_NO>,
477*4882a593Smuzhiyun					<SYSC_IDLE_SMART>,
478*4882a593Smuzhiyun					<SYSC_IDLE_SMART_WKUP>;
479*4882a593Smuzhiyun			clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>;
480*4882a593Smuzhiyun			clock-names = "fck";
481*4882a593Smuzhiyun			#address-cells = <1>;
482*4882a593Smuzhiyun			#size-cells = <1>;
483*4882a593Smuzhiyun			ranges = <0x0 0x48040000 0x1000>;
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun			timer2: timer@0 {
486*4882a593Smuzhiyun				compatible = "ti,dm816-timer";
487*4882a593Smuzhiyun				reg = <0 0x1000>;
488*4882a593Smuzhiyun				interrupts = <68>;
489*4882a593Smuzhiyun				clocks = <&alwon_clkctrl DM816_TIMER2_CLKCTRL 0>;
490*4882a593Smuzhiyun				clock-names = "fck";
491*4882a593Smuzhiyun			};
492*4882a593Smuzhiyun		};
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun		timer3: timer@48042000 {
495*4882a593Smuzhiyun			compatible = "ti,dm816-timer";
496*4882a593Smuzhiyun			reg = <0x48042000 0x2000>;
497*4882a593Smuzhiyun			interrupts = <69>;
498*4882a593Smuzhiyun			ti,hwmods = "timer3";
499*4882a593Smuzhiyun		};
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun		timer4: timer@48044000 {
502*4882a593Smuzhiyun			compatible = "ti,dm816-timer";
503*4882a593Smuzhiyun			reg = <0x48044000 0x2000>;
504*4882a593Smuzhiyun			interrupts = <92>;
505*4882a593Smuzhiyun			ti,hwmods = "timer4";
506*4882a593Smuzhiyun			ti,timer-pwm;
507*4882a593Smuzhiyun		};
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun		timer5: timer@48046000 {
510*4882a593Smuzhiyun			compatible = "ti,dm816-timer";
511*4882a593Smuzhiyun			reg = <0x48046000 0x2000>;
512*4882a593Smuzhiyun			interrupts = <93>;
513*4882a593Smuzhiyun			ti,hwmods = "timer5";
514*4882a593Smuzhiyun			ti,timer-pwm;
515*4882a593Smuzhiyun		};
516*4882a593Smuzhiyun
517*4882a593Smuzhiyun		timer6: timer@48048000 {
518*4882a593Smuzhiyun			compatible = "ti,dm816-timer";
519*4882a593Smuzhiyun			reg = <0x48048000 0x2000>;
520*4882a593Smuzhiyun			interrupts = <94>;
521*4882a593Smuzhiyun			ti,hwmods = "timer6";
522*4882a593Smuzhiyun			ti,timer-pwm;
523*4882a593Smuzhiyun		};
524*4882a593Smuzhiyun
525*4882a593Smuzhiyun		timer7: timer@4804a000 {
526*4882a593Smuzhiyun			compatible = "ti,dm816-timer";
527*4882a593Smuzhiyun			reg = <0x4804a000 0x2000>;
528*4882a593Smuzhiyun			interrupts = <95>;
529*4882a593Smuzhiyun			ti,hwmods = "timer7";
530*4882a593Smuzhiyun			ti,timer-pwm;
531*4882a593Smuzhiyun		};
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun		uart1: uart@48020000 {
534*4882a593Smuzhiyun			compatible = "ti,am3352-uart", "ti,omap3-uart";
535*4882a593Smuzhiyun			ti,hwmods = "uart1";
536*4882a593Smuzhiyun			reg = <0x48020000 0x2000>;
537*4882a593Smuzhiyun			clock-frequency = <48000000>;
538*4882a593Smuzhiyun			interrupts = <72>;
539*4882a593Smuzhiyun			dmas = <&edma 26 0 &edma 27 0>;
540*4882a593Smuzhiyun			dma-names = "tx", "rx";
541*4882a593Smuzhiyun		};
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun		uart2: uart@48022000 {
544*4882a593Smuzhiyun			compatible = "ti,am3352-uart", "ti,omap3-uart";
545*4882a593Smuzhiyun			ti,hwmods = "uart2";
546*4882a593Smuzhiyun			reg = <0x48022000 0x2000>;
547*4882a593Smuzhiyun			clock-frequency = <48000000>;
548*4882a593Smuzhiyun			interrupts = <73>;
549*4882a593Smuzhiyun			dmas = <&edma 28 0 &edma 29 0>;
550*4882a593Smuzhiyun			dma-names = "tx", "rx";
551*4882a593Smuzhiyun		};
552*4882a593Smuzhiyun
553*4882a593Smuzhiyun		uart3: uart@48024000 {
554*4882a593Smuzhiyun			compatible = "ti,am3352-uart", "ti,omap3-uart";
555*4882a593Smuzhiyun			ti,hwmods = "uart3";
556*4882a593Smuzhiyun			reg = <0x48024000 0x2000>;
557*4882a593Smuzhiyun			clock-frequency = <48000000>;
558*4882a593Smuzhiyun			interrupts = <74>;
559*4882a593Smuzhiyun			dmas = <&edma 30 0 &edma 31 0>;
560*4882a593Smuzhiyun			dma-names = "tx", "rx";
561*4882a593Smuzhiyun		};
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun		/* NOTE: USB needs a transceiver driver for phys to work */
564*4882a593Smuzhiyun		usb: usb_otg_hs@47401000 {
565*4882a593Smuzhiyun			compatible = "ti,am33xx-usb";
566*4882a593Smuzhiyun			reg = <0x47401000 0x400000>;
567*4882a593Smuzhiyun			ranges;
568*4882a593Smuzhiyun			#address-cells = <1>;
569*4882a593Smuzhiyun			#size-cells = <1>;
570*4882a593Smuzhiyun			ti,hwmods = "usb_otg_hs";
571*4882a593Smuzhiyun
572*4882a593Smuzhiyun			usb0: usb@47401000 {
573*4882a593Smuzhiyun				compatible = "ti,musb-dm816";
574*4882a593Smuzhiyun				reg = <0x47401400 0x400
575*4882a593Smuzhiyun				       0x47401000 0x200>;
576*4882a593Smuzhiyun				reg-names = "mc", "control";
577*4882a593Smuzhiyun				interrupts = <18>;
578*4882a593Smuzhiyun				interrupt-names = "mc";
579*4882a593Smuzhiyun				dr_mode = "host";
580*4882a593Smuzhiyun				interface-type = <0>;
581*4882a593Smuzhiyun				phys = <&usb_phy0>;
582*4882a593Smuzhiyun				phy-names = "usb2-phy";
583*4882a593Smuzhiyun				mentor,multipoint = <1>;
584*4882a593Smuzhiyun				mentor,num-eps = <16>;
585*4882a593Smuzhiyun				mentor,ram-bits = <12>;
586*4882a593Smuzhiyun				mentor,power = <500>;
587*4882a593Smuzhiyun
588*4882a593Smuzhiyun				dmas = <&cppi41dma  0 0 &cppi41dma  1 0
589*4882a593Smuzhiyun					&cppi41dma  2 0 &cppi41dma  3 0
590*4882a593Smuzhiyun					&cppi41dma  4 0 &cppi41dma  5 0
591*4882a593Smuzhiyun					&cppi41dma  6 0 &cppi41dma  7 0
592*4882a593Smuzhiyun					&cppi41dma  8 0 &cppi41dma  9 0
593*4882a593Smuzhiyun					&cppi41dma 10 0 &cppi41dma 11 0
594*4882a593Smuzhiyun					&cppi41dma 12 0 &cppi41dma 13 0
595*4882a593Smuzhiyun					&cppi41dma 14 0 &cppi41dma  0 1
596*4882a593Smuzhiyun					&cppi41dma  1 1 &cppi41dma  2 1
597*4882a593Smuzhiyun					&cppi41dma  3 1 &cppi41dma  4 1
598*4882a593Smuzhiyun					&cppi41dma  5 1 &cppi41dma  6 1
599*4882a593Smuzhiyun					&cppi41dma  7 1 &cppi41dma  8 1
600*4882a593Smuzhiyun					&cppi41dma  9 1 &cppi41dma 10 1
601*4882a593Smuzhiyun					&cppi41dma 11 1 &cppi41dma 12 1
602*4882a593Smuzhiyun					&cppi41dma 13 1 &cppi41dma 14 1>;
603*4882a593Smuzhiyun				dma-names =
604*4882a593Smuzhiyun					"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
605*4882a593Smuzhiyun					"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
606*4882a593Smuzhiyun					"rx14", "rx15",
607*4882a593Smuzhiyun					"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
608*4882a593Smuzhiyun					"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
609*4882a593Smuzhiyun					"tx14", "tx15";
610*4882a593Smuzhiyun			};
611*4882a593Smuzhiyun
612*4882a593Smuzhiyun			usb1: usb@47401800 {
613*4882a593Smuzhiyun				compatible = "ti,musb-dm816";
614*4882a593Smuzhiyun				reg = <0x47401c00 0x400
615*4882a593Smuzhiyun				       0x47401800 0x200>;
616*4882a593Smuzhiyun				reg-names = "mc", "control";
617*4882a593Smuzhiyun				interrupts = <19>;
618*4882a593Smuzhiyun				interrupt-names = "mc";
619*4882a593Smuzhiyun				dr_mode = "host";
620*4882a593Smuzhiyun				interface-type = <0>;
621*4882a593Smuzhiyun				phys = <&usb_phy1>;
622*4882a593Smuzhiyun				phy-names = "usb2-phy";
623*4882a593Smuzhiyun				mentor,multipoint = <1>;
624*4882a593Smuzhiyun				mentor,num-eps = <16>;
625*4882a593Smuzhiyun				mentor,ram-bits = <12>;
626*4882a593Smuzhiyun				mentor,power = <500>;
627*4882a593Smuzhiyun
628*4882a593Smuzhiyun				dmas = <&cppi41dma 15 0 &cppi41dma 16 0
629*4882a593Smuzhiyun					&cppi41dma 17 0 &cppi41dma 18 0
630*4882a593Smuzhiyun					&cppi41dma 19 0 &cppi41dma 20 0
631*4882a593Smuzhiyun					&cppi41dma 21 0 &cppi41dma 22 0
632*4882a593Smuzhiyun					&cppi41dma 23 0 &cppi41dma 24 0
633*4882a593Smuzhiyun					&cppi41dma 25 0 &cppi41dma 26 0
634*4882a593Smuzhiyun					&cppi41dma 27 0 &cppi41dma 28 0
635*4882a593Smuzhiyun					&cppi41dma 29 0 &cppi41dma 15 1
636*4882a593Smuzhiyun					&cppi41dma 16 1 &cppi41dma 17 1
637*4882a593Smuzhiyun					&cppi41dma 18 1 &cppi41dma 19 1
638*4882a593Smuzhiyun					&cppi41dma 20 1 &cppi41dma 21 1
639*4882a593Smuzhiyun					&cppi41dma 22 1 &cppi41dma 23 1
640*4882a593Smuzhiyun					&cppi41dma 24 1 &cppi41dma 25 1
641*4882a593Smuzhiyun					&cppi41dma 26 1 &cppi41dma 27 1
642*4882a593Smuzhiyun					&cppi41dma 28 1 &cppi41dma 29 1>;
643*4882a593Smuzhiyun				dma-names =
644*4882a593Smuzhiyun					"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
645*4882a593Smuzhiyun					"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
646*4882a593Smuzhiyun					"rx14", "rx15",
647*4882a593Smuzhiyun					"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
648*4882a593Smuzhiyun					"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
649*4882a593Smuzhiyun					"tx14", "tx15";
650*4882a593Smuzhiyun			};
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun			cppi41dma: dma-controller@47402000 {
653*4882a593Smuzhiyun				compatible = "ti,am3359-cppi41";
654*4882a593Smuzhiyun				reg =  <0x47400000 0x1000
655*4882a593Smuzhiyun					0x47402000 0x1000
656*4882a593Smuzhiyun					0x47403000 0x1000
657*4882a593Smuzhiyun					0x47404000 0x4000>;
658*4882a593Smuzhiyun				reg-names = "glue", "controller", "scheduler", "queuemgr";
659*4882a593Smuzhiyun				interrupts = <17>;
660*4882a593Smuzhiyun				interrupt-names = "glue";
661*4882a593Smuzhiyun				#dma-cells = <2>;
662*4882a593Smuzhiyun				#dma-channels = <30>;
663*4882a593Smuzhiyun				#dma-requests = <256>;
664*4882a593Smuzhiyun			};
665*4882a593Smuzhiyun		};
666*4882a593Smuzhiyun
667*4882a593Smuzhiyun		wd_timer2: wd_timer@480c2000 {
668*4882a593Smuzhiyun			compatible = "ti,omap3-wdt";
669*4882a593Smuzhiyun			ti,hwmods = "wd_timer";
670*4882a593Smuzhiyun			reg = <0x480c2000 0x1000>;
671*4882a593Smuzhiyun			interrupts = <0>;
672*4882a593Smuzhiyun		};
673*4882a593Smuzhiyun	};
674*4882a593Smuzhiyun};
675*4882a593Smuzhiyun
676*4882a593Smuzhiyun#include "dm816x-clocks.dtsi"
677*4882a593Smuzhiyun
678*4882a593Smuzhiyun/* Preferred always-on timer for clocksource */
679*4882a593Smuzhiyun&timer1_target {
680*4882a593Smuzhiyun	ti,no-reset-on-init;
681*4882a593Smuzhiyun	ti,no-idle;
682*4882a593Smuzhiyun	timer@0 {
683*4882a593Smuzhiyun		assigned-clocks = <&timer1_fck>;
684*4882a593Smuzhiyun		assigned-clock-parents = <&sys_clkin_ck>;
685*4882a593Smuzhiyun	};
686*4882a593Smuzhiyun};
687*4882a593Smuzhiyun
688*4882a593Smuzhiyun/* Preferred timer for clockevent */
689*4882a593Smuzhiyun&timer2_target {
690*4882a593Smuzhiyun	ti,no-reset-on-init;
691*4882a593Smuzhiyun	ti,no-idle;
692*4882a593Smuzhiyun	timer@0 {
693*4882a593Smuzhiyun		assigned-clocks = <&timer2_fck>;
694*4882a593Smuzhiyun		assigned-clock-parents = <&sys_clkin_ck>;
695*4882a593Smuzhiyun	};
696*4882a593Smuzhiyun};
697