xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/dm8168-evm.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun/dts-v1/;
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun#include "dm816x.dtsi"
5*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h>
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun/ {
8*4882a593Smuzhiyun	model = "DM8168 EVM";
9*4882a593Smuzhiyun	compatible = "ti,dm8168-evm", "ti,dm8168", "ti,dm816";
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun	memory@80000000 {
12*4882a593Smuzhiyun		device_type = "memory";
13*4882a593Smuzhiyun		reg = <0x80000000 0x40000000	/* 1 GB */
14*4882a593Smuzhiyun		       0xc0000000 0x40000000>;	/* 1 GB */
15*4882a593Smuzhiyun	};
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun	/* FDC6331L controlled by SD_POW pin */
18*4882a593Smuzhiyun	vmmcsd_fixed: fixedregulator0 {
19*4882a593Smuzhiyun		compatible = "regulator-fixed";
20*4882a593Smuzhiyun		regulator-name = "vmmcsd_fixed";
21*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
22*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
23*4882a593Smuzhiyun	};
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun	sata_refclk: fixedclock0 {
26*4882a593Smuzhiyun		compatible = "fixed-clock";
27*4882a593Smuzhiyun		#clock-cells = <0>;
28*4882a593Smuzhiyun		clock-frequency = <100000000>;
29*4882a593Smuzhiyun	};
30*4882a593Smuzhiyun};
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun&dm816x_pinmux {
33*4882a593Smuzhiyun	mcspi1_pins: pinmux_mcspi1_pins {
34*4882a593Smuzhiyun		pinctrl-single,pins = <
35*4882a593Smuzhiyun			DM816X_IOPAD(0x0a94, MUX_MODE0)			/* SPI_SCLK */
36*4882a593Smuzhiyun			DM816X_IOPAD(0x0a98, MUX_MODE0)			/* SPI_SCS0 */
37*4882a593Smuzhiyun			DM816X_IOPAD(0x0aa8, MUX_MODE0)			/* SPI_D0 */
38*4882a593Smuzhiyun			DM816X_IOPAD(0x0aac, MUX_MODE0)			/* SPI_D1 */
39*4882a593Smuzhiyun		>;
40*4882a593Smuzhiyun	};
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun	mmc_pins: pinmux_mmc_pins {
43*4882a593Smuzhiyun		pinctrl-single,pins = <
44*4882a593Smuzhiyun			DM816X_IOPAD(0x0a70, MUX_MODE0)			/* SD_POW */
45*4882a593Smuzhiyun			DM816X_IOPAD(0x0a74, MUX_MODE0)			/* SD_CLK */
46*4882a593Smuzhiyun			DM816X_IOPAD(0x0a78, MUX_MODE0)			/* SD_CMD */
47*4882a593Smuzhiyun			DM816X_IOPAD(0x0a7C, MUX_MODE0)			/* SD_DAT0 */
48*4882a593Smuzhiyun			DM816X_IOPAD(0x0a80, MUX_MODE0)			/* SD_DAT1 */
49*4882a593Smuzhiyun			DM816X_IOPAD(0x0a84, MUX_MODE0)			/* SD_DAT2 */
50*4882a593Smuzhiyun			DM816X_IOPAD(0x0a88, MUX_MODE0)			/* SD_DAT2 */
51*4882a593Smuzhiyun			DM816X_IOPAD(0x0a8c, MUX_MODE2)			/* GP1[7] */
52*4882a593Smuzhiyun			DM816X_IOPAD(0x0a90, MUX_MODE2)			/* GP1[8] */
53*4882a593Smuzhiyun		>;
54*4882a593Smuzhiyun	};
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun	usb0_pins: pinmux_usb0_pins {
57*4882a593Smuzhiyun		pinctrl-single,pins = <
58*4882a593Smuzhiyun			DM816X_IOPAD(0x0d04, MUX_MODE0)			/* USB0_DRVVBUS */
59*4882a593Smuzhiyun		>;
60*4882a593Smuzhiyun	};
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun	usb1_pins: pinmux_usb1_pins {
63*4882a593Smuzhiyun		pinctrl-single,pins = <
64*4882a593Smuzhiyun			DM816X_IOPAD(0x0d08, MUX_MODE0)			/* USB1_DRVVBUS */
65*4882a593Smuzhiyun		>;
66*4882a593Smuzhiyun	};
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun	nandflash_pins: nandflash_pins {
69*4882a593Smuzhiyun		pinctrl-single,pins = <
70*4882a593Smuzhiyun			DM816X_IOPAD(0x0b38, PULL_UP | MUX_MODE0)		/* PINCTRL207 GPMC_CS0*/
71*4882a593Smuzhiyun			DM816X_IOPAD(0x0b60, PULL_ENA | MUX_MODE0)		/* PINCTRL217 GPMC_ADV_ALE */
72*4882a593Smuzhiyun			DM816X_IOPAD(0x0b54, PULL_UP | PULL_ENA | MUX_MODE0)	/* PINCTRL214 GPMC_OE_RE */
73*4882a593Smuzhiyun			DM816X_IOPAD(0x0b58, PULL_ENA | MUX_MODE0)		/* PINCTRL215 GPMC_BE0_CLE */
74*4882a593Smuzhiyun			DM816X_IOPAD(0x0b50, PULL_UP | MUX_MODE0)		/* PINCTRL213 GPMC_WE */
75*4882a593Smuzhiyun			DM816X_IOPAD(0x0b6c, MUX_MODE0)				/* PINCTRL220 GPMC_WAIT */
76*4882a593Smuzhiyun			DM816X_IOPAD(0x0be4, PULL_ENA | MUX_MODE0)		/* PINCTRL250 GPMC_CLK */
77*4882a593Smuzhiyun			DM816X_IOPAD(0x0ba4, MUX_MODE0)				/* PINCTRL234 GPMC_D0 */
78*4882a593Smuzhiyun			DM816X_IOPAD(0x0ba8, MUX_MODE0)				/* PINCTRL234 GPMC_D1 */
79*4882a593Smuzhiyun			DM816X_IOPAD(0x0bac, MUX_MODE0)				/* PINCTRL234 GPMC_D2 */
80*4882a593Smuzhiyun			DM816X_IOPAD(0x0bb0, MUX_MODE0)				/* PINCTRL234 GPMC_D3 */
81*4882a593Smuzhiyun			DM816X_IOPAD(0x0bb4, MUX_MODE0)				/* PINCTRL234 GPMC_D4 */
82*4882a593Smuzhiyun			DM816X_IOPAD(0x0bb8, MUX_MODE0)				/* PINCTRL234 GPMC_D5 */
83*4882a593Smuzhiyun			DM816X_IOPAD(0x0bbc, MUX_MODE0)				/* PINCTRL234 GPMC_D6 */
84*4882a593Smuzhiyun			DM816X_IOPAD(0x0bc0, MUX_MODE0)				/* PINCTRL234 GPMC_D7 */
85*4882a593Smuzhiyun			DM816X_IOPAD(0x0bc4, MUX_MODE0)				/* PINCTRL234 GPMC_D8 */
86*4882a593Smuzhiyun			DM816X_IOPAD(0x0bc8, MUX_MODE0)				/* PINCTRL234 GPMC_D9 */
87*4882a593Smuzhiyun			DM816X_IOPAD(0x0bcc, MUX_MODE0)				/* PINCTRL234 GPMC_D10 */
88*4882a593Smuzhiyun			DM816X_IOPAD(0x0bd0, MUX_MODE0)				/* PINCTRL234 GPMC_D11 */
89*4882a593Smuzhiyun			DM816X_IOPAD(0x0bd4, MUX_MODE0)				/* PINCTRL234 GPMC_D12 */
90*4882a593Smuzhiyun			DM816X_IOPAD(0x0bd8, MUX_MODE0)				/* PINCTRL234 GPMC_D13 */
91*4882a593Smuzhiyun			DM816X_IOPAD(0x0bdc, MUX_MODE0)				/* PINCTRL234 GPMC_D14 */
92*4882a593Smuzhiyun			DM816X_IOPAD(0x0be0, MUX_MODE0)				/* PINCTRL234 GPMC_D15 */
93*4882a593Smuzhiyun		>;
94*4882a593Smuzhiyun	};
95*4882a593Smuzhiyun};
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun&i2c1 {
98*4882a593Smuzhiyun	extgpio0: pcf8575@20 {
99*4882a593Smuzhiyun		compatible = "nxp,pcf8575";
100*4882a593Smuzhiyun		reg = <0x20>;
101*4882a593Smuzhiyun		gpio-controller;
102*4882a593Smuzhiyun		#gpio-cells = <2>;
103*4882a593Smuzhiyun	};
104*4882a593Smuzhiyun};
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun&i2c2 {
107*4882a593Smuzhiyun	extgpio1: pcf8575@20 {
108*4882a593Smuzhiyun		compatible = "nxp,pcf8575";
109*4882a593Smuzhiyun		reg = <0x20>;
110*4882a593Smuzhiyun		gpio-controller;
111*4882a593Smuzhiyun		#gpio-cells = <2>;
112*4882a593Smuzhiyun	};
113*4882a593Smuzhiyun};
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun&gpmc {
116*4882a593Smuzhiyun	ranges = <0 0 0x04000000 0x01000000>;	/* CS0: 16MB for NAND */
117*4882a593Smuzhiyun	pinctrl-names = "default";
118*4882a593Smuzhiyun	pinctrl-0 = <&nandflash_pins>;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun	nand@0,0 {
121*4882a593Smuzhiyun		compatible = "ti,omap2-nand";
122*4882a593Smuzhiyun		linux,mtd-name= "micron,mt29f2g16aadwp";
123*4882a593Smuzhiyun		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
124*4882a593Smuzhiyun		interrupt-parent = <&gpmc>;
125*4882a593Smuzhiyun		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
126*4882a593Smuzhiyun			     <1 IRQ_TYPE_NONE>; /* termcount */
127*4882a593Smuzhiyun		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
128*4882a593Smuzhiyun		#address-cells = <1>;
129*4882a593Smuzhiyun		#size-cells = <1>;
130*4882a593Smuzhiyun		ti,nand-ecc-opt = "bch8";
131*4882a593Smuzhiyun		ti,elm-id = <&elm>;
132*4882a593Smuzhiyun		nand-bus-width = <16>;
133*4882a593Smuzhiyun		gpmc,device-width = <2>;
134*4882a593Smuzhiyun		gpmc,sync-clk-ps = <0>;
135*4882a593Smuzhiyun		gpmc,cs-on-ns = <0>;
136*4882a593Smuzhiyun		gpmc,cs-rd-off-ns = <44>;
137*4882a593Smuzhiyun		gpmc,cs-wr-off-ns = <44>;
138*4882a593Smuzhiyun		gpmc,adv-on-ns = <6>;
139*4882a593Smuzhiyun		gpmc,adv-rd-off-ns = <34>;
140*4882a593Smuzhiyun		gpmc,adv-wr-off-ns = <44>;
141*4882a593Smuzhiyun		gpmc,we-on-ns = <0>;
142*4882a593Smuzhiyun		gpmc,we-off-ns = <40>;
143*4882a593Smuzhiyun		gpmc,oe-on-ns = <0>;
144*4882a593Smuzhiyun		gpmc,oe-off-ns = <54>;
145*4882a593Smuzhiyun		gpmc,access-ns = <64>;
146*4882a593Smuzhiyun		gpmc,rd-cycle-ns = <82>;
147*4882a593Smuzhiyun		gpmc,wr-cycle-ns = <82>;
148*4882a593Smuzhiyun		gpmc,bus-turnaround-ns = <0>;
149*4882a593Smuzhiyun		gpmc,cycle2cycle-delay-ns = <0>;
150*4882a593Smuzhiyun		gpmc,clk-activation-ns = <0>;
151*4882a593Smuzhiyun		gpmc,wr-access-ns = <40>;
152*4882a593Smuzhiyun		gpmc,wr-data-mux-bus-ns = <0>;
153*4882a593Smuzhiyun		partition@0 {
154*4882a593Smuzhiyun			label = "X-Loader";
155*4882a593Smuzhiyun			reg = <0 0x80000>;
156*4882a593Smuzhiyun		};
157*4882a593Smuzhiyun		partition@0x80000 {
158*4882a593Smuzhiyun			label = "U-Boot";
159*4882a593Smuzhiyun			reg = <0x80000 0x1c0000>;
160*4882a593Smuzhiyun		};
161*4882a593Smuzhiyun		partition@0x1c0000 {
162*4882a593Smuzhiyun			label = "Environment";
163*4882a593Smuzhiyun			reg = <0x240000 0x40000>;
164*4882a593Smuzhiyun		};
165*4882a593Smuzhiyun		partition@0x280000 {
166*4882a593Smuzhiyun			label = "Kernel";
167*4882a593Smuzhiyun			reg = <0x280000 0x500000>;
168*4882a593Smuzhiyun		};
169*4882a593Smuzhiyun		partition@0x780000 {
170*4882a593Smuzhiyun			label = "Filesystem";
171*4882a593Smuzhiyun			reg = <0x780000 0xf880000>;
172*4882a593Smuzhiyun		};
173*4882a593Smuzhiyun	};
174*4882a593Smuzhiyun};
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun&mcspi1 {
177*4882a593Smuzhiyun	pinctrl-names = "default";
178*4882a593Smuzhiyun	pinctrl-0 = <&mcspi1_pins>;
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun	m25p80@0 {
181*4882a593Smuzhiyun		compatible = "w25x32";
182*4882a593Smuzhiyun		spi-max-frequency = <48000000>;
183*4882a593Smuzhiyun		reg = <0>;
184*4882a593Smuzhiyun		#address-cells = <1>;
185*4882a593Smuzhiyun		#size-cells = <1>;
186*4882a593Smuzhiyun	};
187*4882a593Smuzhiyun};
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun&mmc1 {
190*4882a593Smuzhiyun	pinctrl-names = "default";
191*4882a593Smuzhiyun	pinctrl-0 = <&mmc_pins>;
192*4882a593Smuzhiyun	vmmc-supply = <&vmmcsd_fixed>;
193*4882a593Smuzhiyun	bus-width = <4>;
194*4882a593Smuzhiyun	cd-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
195*4882a593Smuzhiyun	wp-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
196*4882a593Smuzhiyun};
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun/* At least dm8168-evm rev c won't support multipoint, later may */
199*4882a593Smuzhiyun&usb0 {
200*4882a593Smuzhiyun	pinctrl-names = "default";
201*4882a593Smuzhiyun	pinctrl-0 = <&usb0_pins>;
202*4882a593Smuzhiyun	mentor,multipoint = <0>;
203*4882a593Smuzhiyun};
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun&usb1 {
206*4882a593Smuzhiyun	pinctrl-names = "default";
207*4882a593Smuzhiyun	pinctrl-0 = <&usb1_pins>;
208*4882a593Smuzhiyun	mentor,multipoint = <0>;
209*4882a593Smuzhiyun};
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun&sata {
212*4882a593Smuzhiyun	clocks = <&sysclk5_ck>, <&sata_refclk>;
213*4882a593Smuzhiyun};
214