xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/bcm7445.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/arm-gic.h>
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun/ {
5*4882a593Smuzhiyun	#address-cells = <2>;
6*4882a593Smuzhiyun	#size-cells = <2>;
7*4882a593Smuzhiyun	model = "Broadcom STB (bcm7445)";
8*4882a593Smuzhiyun	compatible = "brcm,bcm7445", "brcm,brcmstb";
9*4882a593Smuzhiyun	interrupt-parent = <&gic>;
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun	chosen {
12*4882a593Smuzhiyun		bootargs = "console=ttyS0,115200 earlyprintk";
13*4882a593Smuzhiyun	};
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun	cpus {
16*4882a593Smuzhiyun		#address-cells = <1>;
17*4882a593Smuzhiyun		#size-cells = <0>;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun		cpu@0 {
20*4882a593Smuzhiyun			compatible = "brcm,brahma-b15";
21*4882a593Smuzhiyun			device_type = "cpu";
22*4882a593Smuzhiyun			enable-method = "brcm,brahma-b15";
23*4882a593Smuzhiyun			reg = <0>;
24*4882a593Smuzhiyun		};
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun		cpu@1 {
27*4882a593Smuzhiyun			compatible = "brcm,brahma-b15";
28*4882a593Smuzhiyun			device_type = "cpu";
29*4882a593Smuzhiyun			enable-method = "brcm,brahma-b15";
30*4882a593Smuzhiyun			reg = <1>;
31*4882a593Smuzhiyun		};
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun		cpu@2 {
34*4882a593Smuzhiyun			compatible = "brcm,brahma-b15";
35*4882a593Smuzhiyun			device_type = "cpu";
36*4882a593Smuzhiyun			enable-method = "brcm,brahma-b15";
37*4882a593Smuzhiyun			reg = <2>;
38*4882a593Smuzhiyun		};
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun		cpu@3 {
41*4882a593Smuzhiyun			compatible = "brcm,brahma-b15";
42*4882a593Smuzhiyun			device_type = "cpu";
43*4882a593Smuzhiyun			enable-method = "brcm,brahma-b15";
44*4882a593Smuzhiyun			reg = <3>;
45*4882a593Smuzhiyun		};
46*4882a593Smuzhiyun	};
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun	gic: interrupt-controller@ffd00000 {
49*4882a593Smuzhiyun		compatible = "brcm,brahma-b15-gic", "arm,cortex-a15-gic";
50*4882a593Smuzhiyun		reg = <0x00 0xffd01000 0x00 0x1000>,
51*4882a593Smuzhiyun		      <0x00 0xffd02000 0x00 0x2000>,
52*4882a593Smuzhiyun		      <0x00 0xffd04000 0x00 0x2000>,
53*4882a593Smuzhiyun		      <0x00 0xffd06000 0x00 0x2000>;
54*4882a593Smuzhiyun		interrupt-controller;
55*4882a593Smuzhiyun		#interrupt-cells = <3>;
56*4882a593Smuzhiyun	};
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun	timer {
59*4882a593Smuzhiyun		compatible = "arm,armv7-timer";
60*4882a593Smuzhiyun		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
61*4882a593Smuzhiyun			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
62*4882a593Smuzhiyun			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
63*4882a593Smuzhiyun			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>;
64*4882a593Smuzhiyun	};
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun	rdb@f0000000 {
67*4882a593Smuzhiyun		#address-cells = <1>;
68*4882a593Smuzhiyun		#size-cells = <1>;
69*4882a593Smuzhiyun		compatible = "simple-bus";
70*4882a593Smuzhiyun		ranges = <0 0x00 0xf0000000 0x1000000>;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun		serial@40ab00 {
73*4882a593Smuzhiyun			compatible = "ns16550a";
74*4882a593Smuzhiyun			reg = <0x40ab00 0x20>;
75*4882a593Smuzhiyun			reg-shift = <2>;
76*4882a593Smuzhiyun			reg-io-width = <4>;
77*4882a593Smuzhiyun			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
78*4882a593Smuzhiyun			clock-frequency = <81000000>;
79*4882a593Smuzhiyun		};
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun		sun_top_ctrl: syscon@404000 {
82*4882a593Smuzhiyun			compatible = "brcm,bcm7445-sun-top-ctrl",
83*4882a593Smuzhiyun				     "syscon";
84*4882a593Smuzhiyun			reg = <0x404000 0x51c>;
85*4882a593Smuzhiyun		};
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun		hif_cpubiuctrl: syscon@3e2400 {
88*4882a593Smuzhiyun			compatible = "brcm,bcm7445-hif-cpubiuctrl",
89*4882a593Smuzhiyun				     "syscon";
90*4882a593Smuzhiyun			reg = <0x3e2400 0x5b4>;
91*4882a593Smuzhiyun		};
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun		hif_continuation: syscon@452000 {
94*4882a593Smuzhiyun			compatible = "brcm,bcm7445-hif-continuation",
95*4882a593Smuzhiyun				     "syscon";
96*4882a593Smuzhiyun			reg = <0x452000 0x100>;
97*4882a593Smuzhiyun		};
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun		irq0_intc: interrupt-controller@40a780 {
100*4882a593Smuzhiyun			compatible = "brcm,bcm7120-l2-intc";
101*4882a593Smuzhiyun			interrupt-parent = <&gic>;
102*4882a593Smuzhiyun			#interrupt-cells = <1>;
103*4882a593Smuzhiyun			reg = <0x40a780 0x8>;
104*4882a593Smuzhiyun			interrupt-controller;
105*4882a593Smuzhiyun			interrupts = <GIC_SPI 0x45 0x0>,
106*4882a593Smuzhiyun				     <GIC_SPI 0x43 0x0>;
107*4882a593Smuzhiyun			brcm,int-map-mask = <0x25c>, <0x7000000>;
108*4882a593Smuzhiyun			brcm,int-fwd-mask = <0x70000>;
109*4882a593Smuzhiyun		};
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun		irq0_aon_intc: interrupt-controller@417280 {
112*4882a593Smuzhiyun			compatible = "brcm,bcm7120-l2-intc";
113*4882a593Smuzhiyun			reg = <0x417280 0x8>;
114*4882a593Smuzhiyun			interrupt-parent = <&gic>;
115*4882a593Smuzhiyun			#interrupt-cells = <1>;
116*4882a593Smuzhiyun			interrupt-controller;
117*4882a593Smuzhiyun			interrupts = <GIC_SPI 0x46 0x0>,
118*4882a593Smuzhiyun				     <GIC_SPI 0x44 0x0>,
119*4882a593Smuzhiyun				     <GIC_SPI 0x49 0x0>;
120*4882a593Smuzhiyun			brcm,int-map-mask = <0x1e3 0x18000000 0x100000>;
121*4882a593Smuzhiyun			brcm,int-fwd-mask = <0x0>;
122*4882a593Smuzhiyun			brcm,irq-can-wake;
123*4882a593Smuzhiyun		};
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun		hif_intr2_intc: interrupt-controller@3e1000 {
126*4882a593Smuzhiyun			compatible = "brcm,l2-intc";
127*4882a593Smuzhiyun			reg = <0x3e1000 0x30>;
128*4882a593Smuzhiyun			interrupt-controller;
129*4882a593Smuzhiyun			#interrupt-cells = <1>;
130*4882a593Smuzhiyun			interrupts = <GIC_SPI 0x20 0x0>;
131*4882a593Smuzhiyun			interrupt-parent = <&gic>;
132*4882a593Smuzhiyun			interrupt-names = "hif";
133*4882a593Smuzhiyun		};
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun                aon_pm_l2_intc: interrupt-controller@410640 {
136*4882a593Smuzhiyun			compatible = "brcm,l2-intc";
137*4882a593Smuzhiyun			reg = <0x410640 0x30>;
138*4882a593Smuzhiyun			interrupt-controller;
139*4882a593Smuzhiyun			#interrupt-cells = <1>;
140*4882a593Smuzhiyun			interrupts = <GIC_SPI 0x40 0x0>;
141*4882a593Smuzhiyun			interrupt-parent = <&gic>;
142*4882a593Smuzhiyun			brcm,irq-can-wake;
143*4882a593Smuzhiyun		};
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun		aon-ctrl@410000 {
146*4882a593Smuzhiyun			compatible = "brcm,brcmstb-aon-ctrl";
147*4882a593Smuzhiyun			reg = <0x410000 0x200>, <0x410200 0x400>;
148*4882a593Smuzhiyun			reg-names = "aon-ctrl", "aon-sram";
149*4882a593Smuzhiyun		};
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun		nand_controller: nand-controller@3e2800 {
152*4882a593Smuzhiyun			status = "disabled";
153*4882a593Smuzhiyun			#address-cells = <1>;
154*4882a593Smuzhiyun			#size-cells = <0>;
155*4882a593Smuzhiyun			compatible = "brcm,brcmnand-v7.1", "brcm,brcmnand";
156*4882a593Smuzhiyun			reg-names = "nand", "flash-dma";
157*4882a593Smuzhiyun			reg = <0x3e2800 0x600>, <0x3e3000 0x2c>;
158*4882a593Smuzhiyun			interrupt-parent = <&hif_intr2_intc>;
159*4882a593Smuzhiyun			interrupts = <24>, <4>;
160*4882a593Smuzhiyun			interrupt-names = "nand_ctlrdy", "flash_dma_done";
161*4882a593Smuzhiyun		};
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun		sata@45a000 {
164*4882a593Smuzhiyun			compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci";
165*4882a593Smuzhiyun			reg-names = "ahci", "top-ctrl";
166*4882a593Smuzhiyun			reg = <0x45a000 0xa9c>, <0x458040 0x24>;
167*4882a593Smuzhiyun			interrupts = <GIC_SPI 30 0>;
168*4882a593Smuzhiyun			#address-cells = <1>;
169*4882a593Smuzhiyun			#size-cells = <0>;
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun			sata0: sata-port@0 {
172*4882a593Smuzhiyun				reg = <0>;
173*4882a593Smuzhiyun				phys = <&sata_phy0>;
174*4882a593Smuzhiyun			};
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun			sata1: sata-port@1 {
177*4882a593Smuzhiyun				reg = <1>;
178*4882a593Smuzhiyun				phys = <&sata_phy1>;
179*4882a593Smuzhiyun			};
180*4882a593Smuzhiyun		};
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun		sata_phy: sata-phy@458100 {
183*4882a593Smuzhiyun			compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3";
184*4882a593Smuzhiyun			reg = <0x458100 0x1f00>;
185*4882a593Smuzhiyun			reg-names = "phy";
186*4882a593Smuzhiyun			#address-cells = <0x1>;
187*4882a593Smuzhiyun			#size-cells = <0x0>;
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun			sata_phy0: sata-phy@0 {
190*4882a593Smuzhiyun				reg = <0>;
191*4882a593Smuzhiyun				#phy-cells = <0>;
192*4882a593Smuzhiyun			};
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun			sata_phy1: sata-phy@1 {
195*4882a593Smuzhiyun				reg = <1>;
196*4882a593Smuzhiyun				#phy-cells = <0>;
197*4882a593Smuzhiyun			};
198*4882a593Smuzhiyun		};
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun		upg_gio: gpio@40a700 {
201*4882a593Smuzhiyun			compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
202*4882a593Smuzhiyun			reg = <0x40a700 0x80>;
203*4882a593Smuzhiyun			#gpio-cells = <2>;
204*4882a593Smuzhiyun			#interrupt-cells = <2>;
205*4882a593Smuzhiyun			gpio-controller;
206*4882a593Smuzhiyun			interrupt-controller;
207*4882a593Smuzhiyun			interrupt-parent = <&irq0_intc>;
208*4882a593Smuzhiyun			interrupts = <6>;
209*4882a593Smuzhiyun			brcm,gpio-bank-widths = <32 32 32 24>;
210*4882a593Smuzhiyun		};
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun		upg_gio_aon: gpio@4172c0 {
213*4882a593Smuzhiyun			compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
214*4882a593Smuzhiyun			reg = <0x4172c0 0x40>;
215*4882a593Smuzhiyun			#gpio-cells = <2>;
216*4882a593Smuzhiyun			#interrupt-cells = <2>;
217*4882a593Smuzhiyun			gpio-controller;
218*4882a593Smuzhiyun			interrupt-controller;
219*4882a593Smuzhiyun			interrupts-extended = <&irq0_aon_intc 0x6>,
220*4882a593Smuzhiyun					      <&aon_pm_l2_intc 0x5>;
221*4882a593Smuzhiyun			wakeup-source;
222*4882a593Smuzhiyun			brcm,gpio-bank-widths = <18 4>;
223*4882a593Smuzhiyun		};
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun	};
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun	memory_controllers@f1100000 {
228*4882a593Smuzhiyun		compatible = "simple-bus";
229*4882a593Smuzhiyun		ranges = <0x0 0x0 0xf1100000 0x200000>;
230*4882a593Smuzhiyun		#address-cells = <1>;
231*4882a593Smuzhiyun		#size-cells = <1>;
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun		memc@0 {
234*4882a593Smuzhiyun			compatible = "brcm,brcmstb-memc", "simple-bus";
235*4882a593Smuzhiyun			#address-cells = <1>;
236*4882a593Smuzhiyun			#size-cells = <1>;
237*4882a593Smuzhiyun			ranges = <0x0 0x0 0x80000>;
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun			memc-ddr@2000 {
240*4882a593Smuzhiyun				compatible = "brcm,brcmstb-memc-ddr";
241*4882a593Smuzhiyun				reg = <0x2000 0x800>;
242*4882a593Smuzhiyun			};
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun			ddr-phy@6000 {
245*4882a593Smuzhiyun				compatible = "brcm,brcmstb-ddr-phy-v240.1";
246*4882a593Smuzhiyun				reg = <0x6000 0x21c>;
247*4882a593Smuzhiyun				};
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun			shimphy@8000 {
250*4882a593Smuzhiyun				compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
251*4882a593Smuzhiyun				reg = <0x8000 0xe4>;
252*4882a593Smuzhiyun			};
253*4882a593Smuzhiyun		};
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun		memc@80000 {
256*4882a593Smuzhiyun			compatible = "brcm,brcmstb-memc", "simple-bus";
257*4882a593Smuzhiyun			#address-cells = <1>;
258*4882a593Smuzhiyun			#size-cells = <1>;
259*4882a593Smuzhiyun			ranges = <0x0 0x80000 0x80000>;
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun			memc-ddr@2000 {
262*4882a593Smuzhiyun				compatible = "brcm,brcmstb-memc-ddr";
263*4882a593Smuzhiyun				reg = <0x2000 0x800>;
264*4882a593Smuzhiyun			};
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun			ddr-phy@6000 {
267*4882a593Smuzhiyun				compatible = "brcm,brcmstb-ddr-phy-v240.1";
268*4882a593Smuzhiyun				reg = <0x6000 0x21c>;
269*4882a593Smuzhiyun			};
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun			shimphy@8000 {
272*4882a593Smuzhiyun				compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
273*4882a593Smuzhiyun				reg = <0x8000 0xe4>;
274*4882a593Smuzhiyun			};
275*4882a593Smuzhiyun		};
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun		memc@100000 {
278*4882a593Smuzhiyun			compatible = "brcm,brcmstb-memc", "simple-bus";
279*4882a593Smuzhiyun			#address-cells = <1>;
280*4882a593Smuzhiyun			#size-cells = <1>;
281*4882a593Smuzhiyun			ranges = <0x0 0x100000 0x80000>;
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun			memc-ddr@2000 {
284*4882a593Smuzhiyun				compatible = "brcm,brcmstb-memc-ddr";
285*4882a593Smuzhiyun				reg = <0x2000 0x800>;
286*4882a593Smuzhiyun			};
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun			ddr-phy@6000 {
289*4882a593Smuzhiyun				compatible = "brcm,brcmstb-ddr-phy-v240.1";
290*4882a593Smuzhiyun				reg = <0x6000 0x21c>;
291*4882a593Smuzhiyun			};
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun			shimphy@8000 {
294*4882a593Smuzhiyun				compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
295*4882a593Smuzhiyun				reg = <0x8000 0xe4>;
296*4882a593Smuzhiyun			};
297*4882a593Smuzhiyun		};
298*4882a593Smuzhiyun	};
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun	sram@ffe00000 {
301*4882a593Smuzhiyun		compatible = "brcm,boot-sram", "mmio-sram";
302*4882a593Smuzhiyun		reg = <0x0 0xffe00000 0x0 0x10000>;
303*4882a593Smuzhiyun	};
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun	smpboot {
306*4882a593Smuzhiyun		compatible = "brcm,brcmstb-smpboot";
307*4882a593Smuzhiyun		syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>;
308*4882a593Smuzhiyun		syscon-cont = <&hif_continuation>;
309*4882a593Smuzhiyun	};
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun	reboot {
312*4882a593Smuzhiyun		compatible = "brcm,brcmstb-reboot";
313*4882a593Smuzhiyun		syscon = <&sun_top_ctrl 0x304 0x308>;
314*4882a593Smuzhiyun	};
315*4882a593Smuzhiyun};
316