xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright 2017 Luxul Inc.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun/dts-v1/;
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun#include "bcm53573.dtsi"
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun/ {
11*4882a593Smuzhiyun	compatible = "luxul,xap-810-v1", "brcm,bcm47189", "brcm,bcm53573";
12*4882a593Smuzhiyun	model = "Luxul XAP-810 V1";
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun	chosen {
15*4882a593Smuzhiyun		bootargs = "earlycon";
16*4882a593Smuzhiyun	};
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun	memory@0 {
19*4882a593Smuzhiyun		device_type = "memory";
20*4882a593Smuzhiyun		reg = <0x00000000 0x08000000>;
21*4882a593Smuzhiyun	};
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun	leds {
24*4882a593Smuzhiyun		compatible = "gpio-leds";
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun		5ghz {
27*4882a593Smuzhiyun			label = "bcm53xx:blue:5ghz";
28*4882a593Smuzhiyun			gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>;
29*4882a593Smuzhiyun			linux,default-trigger = "default-off";
30*4882a593Smuzhiyun		};
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun		system {
33*4882a593Smuzhiyun			label = "bcm53xx:green:system";
34*4882a593Smuzhiyun			gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>;
35*4882a593Smuzhiyun			linux,default-trigger = "timer";
36*4882a593Smuzhiyun		};
37*4882a593Smuzhiyun	};
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun	pcie0_leds {
40*4882a593Smuzhiyun		compatible = "gpio-leds";
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun		2ghz {
43*4882a593Smuzhiyun			label = "bcm53xx:blue:2ghz";
44*4882a593Smuzhiyun			gpios = <&pcie0_chipcommon 3 GPIO_ACTIVE_HIGH>;
45*4882a593Smuzhiyun			linux,default-trigger = "default-off";
46*4882a593Smuzhiyun		};
47*4882a593Smuzhiyun	};
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun	gpio-keys {
50*4882a593Smuzhiyun		compatible = "gpio-keys";
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun		restart {
53*4882a593Smuzhiyun			label = "Reset";
54*4882a593Smuzhiyun			linux,code = <KEY_RESTART>;
55*4882a593Smuzhiyun			gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
56*4882a593Smuzhiyun		};
57*4882a593Smuzhiyun	};
58*4882a593Smuzhiyun};
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun&pcie0 {
61*4882a593Smuzhiyun	ranges = <0x00000000 0 0 0 0 0x00100000>;
62*4882a593Smuzhiyun	#address-cells = <3>;
63*4882a593Smuzhiyun	#size-cells = <2>;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun	bridge@0,0,0 {
66*4882a593Smuzhiyun		reg = <0x0000 0 0 0 0>;
67*4882a593Smuzhiyun		ranges = <0x00000000 0 0 0 0 0 0 0x00100000>;
68*4882a593Smuzhiyun		#address-cells = <3>;
69*4882a593Smuzhiyun		#size-cells = <2>;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun		wifi@0,1,0 {
72*4882a593Smuzhiyun			reg = <0x0000 0 0 0 0>;
73*4882a593Smuzhiyun			ranges = <0x00000000 0 0 0 0x00100000>;
74*4882a593Smuzhiyun			#address-cells = <1>;
75*4882a593Smuzhiyun			#size-cells = <1>;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun			pcie0_chipcommon: chipcommon@0 {
78*4882a593Smuzhiyun				reg = <0 0x1000>;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun				gpio-controller;
81*4882a593Smuzhiyun				#gpio-cells = <2>;
82*4882a593Smuzhiyun			};
83*4882a593Smuzhiyun		};
84*4882a593Smuzhiyun	};
85*4882a593Smuzhiyun};
86