1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Broadcom BCM470X / BCM5301X ARM platform code. 3*4882a593Smuzhiyun * DTS for BCM4708 SoC. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Licensed under the GNU/GPL. See COPYING for details. 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun#include "bcm5301x.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun compatible = "brcm,bcm4708"; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun aliases { 16*4882a593Smuzhiyun serial0 = &uart0; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun chosen { 20*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun cpus { 24*4882a593Smuzhiyun #address-cells = <1>; 25*4882a593Smuzhiyun #size-cells = <0>; 26*4882a593Smuzhiyun enable-method = "brcm,bcm-nsp-smp"; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun cpu@0 { 29*4882a593Smuzhiyun device_type = "cpu"; 30*4882a593Smuzhiyun compatible = "arm,cortex-a9"; 31*4882a593Smuzhiyun next-level-cache = <&L2>; 32*4882a593Smuzhiyun reg = <0x0>; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun cpu@1 { 36*4882a593Smuzhiyun device_type = "cpu"; 37*4882a593Smuzhiyun compatible = "arm,cortex-a9"; 38*4882a593Smuzhiyun next-level-cache = <&L2>; 39*4882a593Smuzhiyun secondary-boot-reg = <0xffff0400>; 40*4882a593Smuzhiyun reg = <0x1>; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun}; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun&uart0 { 47*4882a593Smuzhiyun status = "okay"; 48*4882a593Smuzhiyun}; 49