xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/bcm23550.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun *  BSD LICENSE
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun *  Copyright(c) 2016 Broadcom.  All rights reserved.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun *  Redistribution and use in source and binary forms, with or without
7*4882a593Smuzhiyun *  modification, are permitted provided that the following conditions
8*4882a593Smuzhiyun *  are met:
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun *    * Redistributions of source code must retain the above copyright
11*4882a593Smuzhiyun *      notice, this list of conditions and the following disclaimer.
12*4882a593Smuzhiyun *    * Redistributions in binary form must reproduce the above copyright
13*4882a593Smuzhiyun *      notice, this list of conditions and the following disclaimer in
14*4882a593Smuzhiyun *      the documentation and/or other materials provided with the
15*4882a593Smuzhiyun *      distribution.
16*4882a593Smuzhiyun *    * Neither the name of Broadcom Corporation nor the names of its
17*4882a593Smuzhiyun *      contributors may be used to endorse or promote products derived
18*4882a593Smuzhiyun *      from this software without specific prior written permission.
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21*4882a593Smuzhiyun *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22*4882a593Smuzhiyun *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23*4882a593Smuzhiyun *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24*4882a593Smuzhiyun *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25*4882a593Smuzhiyun *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26*4882a593Smuzhiyun *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27*4882a593Smuzhiyun *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28*4882a593Smuzhiyun *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29*4882a593Smuzhiyun *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30*4882a593Smuzhiyun * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31*4882a593Smuzhiyun */
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/arm-gic.h>
34*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h>
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun/* BCM23550 and BCM21664 have almost identical clocks */
37*4882a593Smuzhiyun#include "dt-bindings/clock/bcm21664.h"
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun/ {
40*4882a593Smuzhiyun	#address-cells = <1>;
41*4882a593Smuzhiyun	#size-cells = <1>;
42*4882a593Smuzhiyun	model = "BCM23550 SoC";
43*4882a593Smuzhiyun	compatible = "brcm,bcm23550";
44*4882a593Smuzhiyun	interrupt-parent = <&gic>;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun	cpus {
47*4882a593Smuzhiyun		#address-cells = <1>;
48*4882a593Smuzhiyun		#size-cells = <0>;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun		cpu0: cpu@0 {
51*4882a593Smuzhiyun			device_type = "cpu";
52*4882a593Smuzhiyun			compatible = "arm,cortex-a7";
53*4882a593Smuzhiyun			reg = <0>;
54*4882a593Smuzhiyun			clock-frequency = <1000000000>;
55*4882a593Smuzhiyun		};
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun		cpu1: cpu@1 {
58*4882a593Smuzhiyun			device_type = "cpu";
59*4882a593Smuzhiyun			compatible = "arm,cortex-a7";
60*4882a593Smuzhiyun			enable-method = "brcm,bcm23550";
61*4882a593Smuzhiyun			secondary-boot-reg = <0x35004178>;
62*4882a593Smuzhiyun			reg = <1>;
63*4882a593Smuzhiyun			clock-frequency = <1000000000>;
64*4882a593Smuzhiyun		};
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun		cpu2: cpu@2 {
67*4882a593Smuzhiyun			device_type = "cpu";
68*4882a593Smuzhiyun			compatible = "arm,cortex-a7";
69*4882a593Smuzhiyun			enable-method = "brcm,bcm23550";
70*4882a593Smuzhiyun			secondary-boot-reg = <0x35004178>;
71*4882a593Smuzhiyun			reg = <2>;
72*4882a593Smuzhiyun			clock-frequency = <1000000000>;
73*4882a593Smuzhiyun		};
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun		cpu3: cpu@3 {
76*4882a593Smuzhiyun			device_type = "cpu";
77*4882a593Smuzhiyun			compatible = "arm,cortex-a7";
78*4882a593Smuzhiyun			enable-method = "brcm,bcm23550";
79*4882a593Smuzhiyun			secondary-boot-reg = <0x35004178>;
80*4882a593Smuzhiyun			reg = <3>;
81*4882a593Smuzhiyun			clock-frequency = <1000000000>;
82*4882a593Smuzhiyun		};
83*4882a593Smuzhiyun	};
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun	/* Hub bus */
86*4882a593Smuzhiyun	hub@34000000 {
87*4882a593Smuzhiyun		compatible = "simple-bus";
88*4882a593Smuzhiyun		ranges = <0 0x34000000 0x102f83ac>;
89*4882a593Smuzhiyun		#address-cells = <1>;
90*4882a593Smuzhiyun		#size-cells = <1>;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun		smc@4e000 {
93*4882a593Smuzhiyun			compatible = "brcm,bcm23550-smc", "brcm,kona-smc";
94*4882a593Smuzhiyun			reg = <0x0004e000 0x400>; /* 1 KiB in SRAM */
95*4882a593Smuzhiyun		};
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun		resetmgr: reset-controller@1001f00 {
98*4882a593Smuzhiyun			compatible = "brcm,bcm21664-resetmgr";
99*4882a593Smuzhiyun			reg = <0x01001f00 0x24>;
100*4882a593Smuzhiyun		};
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun		gpio: gpio@1003000 {
103*4882a593Smuzhiyun			compatible = "brcm,bcm23550-gpio", "brcm,kona-gpio";
104*4882a593Smuzhiyun			reg = <0x01003000 0x524>;
105*4882a593Smuzhiyun			interrupts =
106*4882a593Smuzhiyun			       <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH
107*4882a593Smuzhiyun				GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH
108*4882a593Smuzhiyun				GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH
109*4882a593Smuzhiyun				GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
110*4882a593Smuzhiyun			#gpio-cells = <2>;
111*4882a593Smuzhiyun			#interrupt-cells = <2>;
112*4882a593Smuzhiyun			gpio-controller;
113*4882a593Smuzhiyun			interrupt-controller;
114*4882a593Smuzhiyun		};
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun		timer@1006000 {
117*4882a593Smuzhiyun			compatible = "brcm,kona-timer";
118*4882a593Smuzhiyun			reg = <0x01006000 0x1c>;
119*4882a593Smuzhiyun			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
120*4882a593Smuzhiyun			clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>;
121*4882a593Smuzhiyun		};
122*4882a593Smuzhiyun	};
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun	/* Slaves bus */
125*4882a593Smuzhiyun	slaves@3e000000 {
126*4882a593Smuzhiyun		compatible = "simple-bus";
127*4882a593Smuzhiyun		ranges = <0 0x3e000000 0x0001c070>;
128*4882a593Smuzhiyun		#address-cells = <1>;
129*4882a593Smuzhiyun		#size-cells = <1>;
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun		uartb: serial@0 {
132*4882a593Smuzhiyun			compatible = "snps,dw-apb-uart";
133*4882a593Smuzhiyun			status = "disabled";
134*4882a593Smuzhiyun			reg = <0x00000000 0x118>;
135*4882a593Smuzhiyun			clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>;
136*4882a593Smuzhiyun			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
137*4882a593Smuzhiyun			reg-shift = <2>;
138*4882a593Smuzhiyun			reg-io-width = <4>;
139*4882a593Smuzhiyun		};
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun		uartb2: serial@1000 {
142*4882a593Smuzhiyun			compatible = "snps,dw-apb-uart";
143*4882a593Smuzhiyun			status = "disabled";
144*4882a593Smuzhiyun			reg = <0x00001000 0x118>;
145*4882a593Smuzhiyun			clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>;
146*4882a593Smuzhiyun			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
147*4882a593Smuzhiyun			reg-shift = <2>;
148*4882a593Smuzhiyun			reg-io-width = <4>;
149*4882a593Smuzhiyun		};
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun		uartb3: serial@2000 {
152*4882a593Smuzhiyun			compatible = "snps,dw-apb-uart";
153*4882a593Smuzhiyun			status = "disabled";
154*4882a593Smuzhiyun			reg = <0x00002000 0x118>;
155*4882a593Smuzhiyun			clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>;
156*4882a593Smuzhiyun			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
157*4882a593Smuzhiyun			reg-shift = <2>;
158*4882a593Smuzhiyun			reg-io-width = <4>;
159*4882a593Smuzhiyun		};
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun		bsc1: i2c@16000 {
162*4882a593Smuzhiyun			compatible = "brcm,kona-i2c";
163*4882a593Smuzhiyun			reg = <0x00016000 0x70>;
164*4882a593Smuzhiyun			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
165*4882a593Smuzhiyun			#address-cells = <1>;
166*4882a593Smuzhiyun			#size-cells = <0>;
167*4882a593Smuzhiyun			clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>;
168*4882a593Smuzhiyun			status = "disabled";
169*4882a593Smuzhiyun		};
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun		bsc2: i2c@17000 {
172*4882a593Smuzhiyun			compatible = "brcm,kona-i2c";
173*4882a593Smuzhiyun			reg = <0x00017000 0x70>;
174*4882a593Smuzhiyun			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
175*4882a593Smuzhiyun			#address-cells = <1>;
176*4882a593Smuzhiyun			#size-cells = <0>;
177*4882a593Smuzhiyun			clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>;
178*4882a593Smuzhiyun			status = "disabled";
179*4882a593Smuzhiyun		};
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun		bsc3: i2c@18000 {
182*4882a593Smuzhiyun			compatible = "brcm,kona-i2c";
183*4882a593Smuzhiyun			reg = <0x00018000 0x70>;
184*4882a593Smuzhiyun			interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
185*4882a593Smuzhiyun			#address-cells = <1>;
186*4882a593Smuzhiyun			#size-cells = <0>;
187*4882a593Smuzhiyun			clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>;
188*4882a593Smuzhiyun			status = "disabled";
189*4882a593Smuzhiyun		};
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun		bsc4: i2c@1c000 {
192*4882a593Smuzhiyun			compatible = "brcm,kona-i2c";
193*4882a593Smuzhiyun			reg = <0x0001c000 0x70>;
194*4882a593Smuzhiyun			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
195*4882a593Smuzhiyun			#address-cells = <1>;
196*4882a593Smuzhiyun			#size-cells = <0>;
197*4882a593Smuzhiyun			clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>;
198*4882a593Smuzhiyun			status = "disabled";
199*4882a593Smuzhiyun		};
200*4882a593Smuzhiyun	};
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun	/* Apps bus */
203*4882a593Smuzhiyun	apps@3e300000 {
204*4882a593Smuzhiyun		compatible = "simple-bus";
205*4882a593Smuzhiyun		ranges = <0 0x3e300000 0x01b77000>;
206*4882a593Smuzhiyun		#address-cells = <1>;
207*4882a593Smuzhiyun		#size-cells = <1>;
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun		usbotg: usb@e20000 {
210*4882a593Smuzhiyun			compatible = "snps,dwc2";
211*4882a593Smuzhiyun			reg = <0x00e20000 0x10000>;
212*4882a593Smuzhiyun			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
213*4882a593Smuzhiyun			clocks = <&usb_otg_ahb_clk>;
214*4882a593Smuzhiyun			clock-names = "otg";
215*4882a593Smuzhiyun			phys = <&usbphy>;
216*4882a593Smuzhiyun			phy-names = "usb2-phy";
217*4882a593Smuzhiyun			status = "disabled";
218*4882a593Smuzhiyun		};
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun		usbphy: usb-phy@e30000 {
221*4882a593Smuzhiyun			compatible = "brcm,kona-usb2-phy";
222*4882a593Smuzhiyun			reg = <0x00e30000 0x28>;
223*4882a593Smuzhiyun			#phy-cells = <0>;
224*4882a593Smuzhiyun			status = "disabled";
225*4882a593Smuzhiyun		};
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun		sdio1: sdio@e80000 {
228*4882a593Smuzhiyun			compatible = "brcm,kona-sdhci";
229*4882a593Smuzhiyun			reg = <0x00e80000 0x801c>;
230*4882a593Smuzhiyun			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
231*4882a593Smuzhiyun			clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>;
232*4882a593Smuzhiyun			status = "disabled";
233*4882a593Smuzhiyun		};
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun		sdio2: sdio@e90000 {
236*4882a593Smuzhiyun			compatible = "brcm,kona-sdhci";
237*4882a593Smuzhiyun			reg = <0x00e90000 0x801c>;
238*4882a593Smuzhiyun			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
239*4882a593Smuzhiyun			clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>;
240*4882a593Smuzhiyun			status = "disabled";
241*4882a593Smuzhiyun		};
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun		sdio3: sdio@ea0000 {
244*4882a593Smuzhiyun			compatible = "brcm,kona-sdhci";
245*4882a593Smuzhiyun			reg = <0x00ea0000 0x801c>;
246*4882a593Smuzhiyun			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
247*4882a593Smuzhiyun			clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>;
248*4882a593Smuzhiyun			status = "disabled";
249*4882a593Smuzhiyun		};
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun		sdio4: sdio@eb0000 {
252*4882a593Smuzhiyun			compatible = "brcm,kona-sdhci";
253*4882a593Smuzhiyun			reg = <0x00eb0000 0x801c>;
254*4882a593Smuzhiyun			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
255*4882a593Smuzhiyun			clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>;
256*4882a593Smuzhiyun			status = "disabled";
257*4882a593Smuzhiyun		};
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun		cdc: cdc@1b0e000 {
260*4882a593Smuzhiyun			compatible = "brcm,bcm23550-cdc";
261*4882a593Smuzhiyun			reg = <0x01b0e000 0x78>;
262*4882a593Smuzhiyun		};
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun		gic: interrupt-controller@1b21000 {
265*4882a593Smuzhiyun			compatible = "arm,cortex-a9-gic";
266*4882a593Smuzhiyun			#interrupt-cells = <3>;
267*4882a593Smuzhiyun			#address-cells = <0>;
268*4882a593Smuzhiyun			interrupt-controller;
269*4882a593Smuzhiyun			reg = <0x01b21000 0x1000>,
270*4882a593Smuzhiyun			      <0x01b22000 0x1000>;
271*4882a593Smuzhiyun		};
272*4882a593Smuzhiyun	};
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun	clocks {
275*4882a593Smuzhiyun		#address-cells = <1>;
276*4882a593Smuzhiyun		#size-cells = <1>;
277*4882a593Smuzhiyun		ranges;
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun		/*
280*4882a593Smuzhiyun		 * Fixed clocks are defined before CCUs whose
281*4882a593Smuzhiyun		 * clocks may depend on them.
282*4882a593Smuzhiyun		 */
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun		ref_32k_clk: ref_32k {
285*4882a593Smuzhiyun			#clock-cells = <0>;
286*4882a593Smuzhiyun			compatible = "fixed-clock";
287*4882a593Smuzhiyun			clock-frequency = <32768>;
288*4882a593Smuzhiyun		};
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun		bbl_32k_clk: bbl_32k {
291*4882a593Smuzhiyun			#clock-cells = <0>;
292*4882a593Smuzhiyun			compatible = "fixed-clock";
293*4882a593Smuzhiyun			clock-frequency = <32768>;
294*4882a593Smuzhiyun		};
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun		ref_13m_clk: ref_13m {
297*4882a593Smuzhiyun			#clock-cells = <0>;
298*4882a593Smuzhiyun			compatible = "fixed-clock";
299*4882a593Smuzhiyun			clock-frequency = <13000000>;
300*4882a593Smuzhiyun		};
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun		var_13m_clk: var_13m {
303*4882a593Smuzhiyun			#clock-cells = <0>;
304*4882a593Smuzhiyun			compatible = "fixed-clock";
305*4882a593Smuzhiyun			clock-frequency = <13000000>;
306*4882a593Smuzhiyun		};
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun		dft_19_5m_clk: dft_19_5m {
309*4882a593Smuzhiyun			#clock-cells = <0>;
310*4882a593Smuzhiyun			compatible = "fixed-clock";
311*4882a593Smuzhiyun			clock-frequency = <19500000>;
312*4882a593Smuzhiyun		};
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun		ref_crystal_clk: ref_crystal {
315*4882a593Smuzhiyun			#clock-cells = <0>;
316*4882a593Smuzhiyun			compatible = "fixed-clock";
317*4882a593Smuzhiyun			clock-frequency = <26000000>;
318*4882a593Smuzhiyun		};
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun		ref_52m_clk: ref_52m {
321*4882a593Smuzhiyun			#clock-cells = <0>;
322*4882a593Smuzhiyun			compatible = "fixed-clock";
323*4882a593Smuzhiyun			clock-frequency = <52000000>;
324*4882a593Smuzhiyun		};
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun		var_52m_clk: var_52m {
327*4882a593Smuzhiyun			#clock-cells = <0>;
328*4882a593Smuzhiyun			compatible = "fixed-clock";
329*4882a593Smuzhiyun			clock-frequency = <52000000>;
330*4882a593Smuzhiyun		};
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun		usb_otg_ahb_clk: usb_otg_ahb {
333*4882a593Smuzhiyun			#clock-cells = <0>;
334*4882a593Smuzhiyun			compatible = "fixed-clock";
335*4882a593Smuzhiyun			clock-frequency = <52000000>;
336*4882a593Smuzhiyun		};
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun		ref_96m_clk: ref_96m {
339*4882a593Smuzhiyun			#clock-cells = <0>;
340*4882a593Smuzhiyun			compatible = "fixed-clock";
341*4882a593Smuzhiyun			clock-frequency = <96000000>;
342*4882a593Smuzhiyun		};
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun		var_96m_clk: var_96m {
345*4882a593Smuzhiyun			#clock-cells = <0>;
346*4882a593Smuzhiyun			compatible = "fixed-clock";
347*4882a593Smuzhiyun			clock-frequency = <96000000>;
348*4882a593Smuzhiyun		};
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun		ref_104m_clk: ref_104m {
351*4882a593Smuzhiyun			#clock-cells = <0>;
352*4882a593Smuzhiyun			compatible = "fixed-clock";
353*4882a593Smuzhiyun			clock-frequency = <104000000>;
354*4882a593Smuzhiyun		};
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun		var_104m_clk: var_104m {
357*4882a593Smuzhiyun			#clock-cells = <0>;
358*4882a593Smuzhiyun			compatible = "fixed-clock";
359*4882a593Smuzhiyun			clock-frequency = <104000000>;
360*4882a593Smuzhiyun		};
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun		ref_156m_clk: ref_156m {
363*4882a593Smuzhiyun			#clock-cells = <0>;
364*4882a593Smuzhiyun			compatible = "fixed-clock";
365*4882a593Smuzhiyun			clock-frequency = <156000000>;
366*4882a593Smuzhiyun		};
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun		var_156m_clk: var_156m {
369*4882a593Smuzhiyun			#clock-cells = <0>;
370*4882a593Smuzhiyun			compatible = "fixed-clock";
371*4882a593Smuzhiyun			clock-frequency = <156000000>;
372*4882a593Smuzhiyun		};
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun		root_ccu: root_ccu@35001000 {
375*4882a593Smuzhiyun			compatible = BCM21664_DT_ROOT_CCU_COMPAT;
376*4882a593Smuzhiyun			reg = <0x35001000 0x0f00>;
377*4882a593Smuzhiyun			#clock-cells = <1>;
378*4882a593Smuzhiyun			clock-output-names = "frac_1m";
379*4882a593Smuzhiyun		};
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun		aon_ccu: aon_ccu@35002000 {
382*4882a593Smuzhiyun			compatible = BCM21664_DT_AON_CCU_COMPAT;
383*4882a593Smuzhiyun			reg = <0x35002000 0x0f00>;
384*4882a593Smuzhiyun			#clock-cells = <1>;
385*4882a593Smuzhiyun			clock-output-names = "hub_timer";
386*4882a593Smuzhiyun		};
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun		slave_ccu: slave_ccu@3e011000 {
389*4882a593Smuzhiyun			compatible = BCM21664_DT_SLAVE_CCU_COMPAT;
390*4882a593Smuzhiyun			reg = <0x3e011000 0x0f00>;
391*4882a593Smuzhiyun			#clock-cells = <1>;
392*4882a593Smuzhiyun			clock-output-names = "uartb",
393*4882a593Smuzhiyun					     "uartb2",
394*4882a593Smuzhiyun					     "uartb3",
395*4882a593Smuzhiyun					     "bsc1",
396*4882a593Smuzhiyun					     "bsc2",
397*4882a593Smuzhiyun					     "bsc3",
398*4882a593Smuzhiyun					     "bsc4";
399*4882a593Smuzhiyun		};
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun		master_ccu: master_ccu@3f001000 {
402*4882a593Smuzhiyun			compatible = BCM21664_DT_MASTER_CCU_COMPAT;
403*4882a593Smuzhiyun			reg = <0x3f001000 0x0f00>;
404*4882a593Smuzhiyun			#clock-cells = <1>;
405*4882a593Smuzhiyun			clock-output-names = "sdio1",
406*4882a593Smuzhiyun					     "sdio2",
407*4882a593Smuzhiyun					     "sdio3",
408*4882a593Smuzhiyun					     "sdio4",
409*4882a593Smuzhiyun					     "sdio1_sleep",
410*4882a593Smuzhiyun					     "sdio2_sleep",
411*4882a593Smuzhiyun					     "sdio3_sleep",
412*4882a593Smuzhiyun					     "sdio4_sleep";
413*4882a593Smuzhiyun		};
414*4882a593Smuzhiyun	};
415*4882a593Smuzhiyun};
416