1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2014 Broadcom Corporation 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or 5*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License as 6*4882a593Smuzhiyun * published by the Free Software Foundation version 2. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * This program is distributed "as is" WITHOUT ANY WARRANTY of any 9*4882a593Smuzhiyun * kind, whether express or implied; without even the implied warranty 10*4882a593Smuzhiyun * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11*4882a593Smuzhiyun * GNU General Public License for more details. 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/arm-gic.h> 15*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun#include "dt-bindings/clock/bcm21664.h" 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun/ { 20*4882a593Smuzhiyun #address-cells = <1>; 21*4882a593Smuzhiyun #size-cells = <1>; 22*4882a593Smuzhiyun model = "BCM21664 SoC"; 23*4882a593Smuzhiyun compatible = "brcm,bcm21664"; 24*4882a593Smuzhiyun interrupt-parent = <&gic>; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun chosen { 27*4882a593Smuzhiyun bootargs = "console=ttyS0,115200n8"; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun cpus { 31*4882a593Smuzhiyun #address-cells = <1>; 32*4882a593Smuzhiyun #size-cells = <0>; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun cpu0: cpu@0 { 35*4882a593Smuzhiyun device_type = "cpu"; 36*4882a593Smuzhiyun compatible = "arm,cortex-a9"; 37*4882a593Smuzhiyun reg = <0>; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun cpu1: cpu@1 { 41*4882a593Smuzhiyun device_type = "cpu"; 42*4882a593Smuzhiyun compatible = "arm,cortex-a9"; 43*4882a593Smuzhiyun enable-method = "brcm,bcm11351-cpu-method"; 44*4882a593Smuzhiyun secondary-boot-reg = <0x35004178>; 45*4882a593Smuzhiyun reg = <1>; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun gic: interrupt-controller@3ff00100 { 50*4882a593Smuzhiyun compatible = "arm,cortex-a9-gic"; 51*4882a593Smuzhiyun #interrupt-cells = <3>; 52*4882a593Smuzhiyun #address-cells = <0>; 53*4882a593Smuzhiyun interrupt-controller; 54*4882a593Smuzhiyun reg = <0x3ff01000 0x1000>, 55*4882a593Smuzhiyun <0x3ff00100 0x100>; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun smc@3404e000 { 59*4882a593Smuzhiyun compatible = "brcm,bcm21664-smc", "brcm,kona-smc"; 60*4882a593Smuzhiyun reg = <0x3404e000 0x400>; /* 1 KiB in SRAM */ 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun uart@3e000000 { 64*4882a593Smuzhiyun compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; 65*4882a593Smuzhiyun status = "disabled"; 66*4882a593Smuzhiyun reg = <0x3e000000 0x118>; 67*4882a593Smuzhiyun clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>; 68*4882a593Smuzhiyun interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 69*4882a593Smuzhiyun reg-shift = <2>; 70*4882a593Smuzhiyun reg-io-width = <4>; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun uart@3e001000 { 74*4882a593Smuzhiyun compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; 75*4882a593Smuzhiyun status = "disabled"; 76*4882a593Smuzhiyun reg = <0x3e001000 0x118>; 77*4882a593Smuzhiyun clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>; 78*4882a593Smuzhiyun interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 79*4882a593Smuzhiyun reg-shift = <2>; 80*4882a593Smuzhiyun reg-io-width = <4>; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun uart@3e002000 { 84*4882a593Smuzhiyun compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; 85*4882a593Smuzhiyun status = "disabled"; 86*4882a593Smuzhiyun reg = <0x3e002000 0x118>; 87*4882a593Smuzhiyun clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>; 88*4882a593Smuzhiyun interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 89*4882a593Smuzhiyun reg-shift = <2>; 90*4882a593Smuzhiyun reg-io-width = <4>; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun L2: cache-controller@3ff20000 { 94*4882a593Smuzhiyun compatible = "arm,pl310-cache"; 95*4882a593Smuzhiyun reg = <0x3ff20000 0x1000>; 96*4882a593Smuzhiyun cache-unified; 97*4882a593Smuzhiyun cache-level = <2>; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun brcm,resetmgr@35001f00 { 101*4882a593Smuzhiyun compatible = "brcm,bcm21664-resetmgr"; 102*4882a593Smuzhiyun reg = <0x35001f00 0x24>; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun timer@35006000 { 106*4882a593Smuzhiyun compatible = "brcm,kona-timer"; 107*4882a593Smuzhiyun reg = <0x35006000 0x1c>; 108*4882a593Smuzhiyun interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 109*4882a593Smuzhiyun clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun gpio: gpio@35003000 { 113*4882a593Smuzhiyun compatible = "brcm,bcm21664-gpio", "brcm,kona-gpio"; 114*4882a593Smuzhiyun reg = <0x35003000 0x524>; 115*4882a593Smuzhiyun interrupts = 116*4882a593Smuzhiyun <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 117*4882a593Smuzhiyun GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 118*4882a593Smuzhiyun GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 119*4882a593Smuzhiyun GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 120*4882a593Smuzhiyun #gpio-cells = <2>; 121*4882a593Smuzhiyun #interrupt-cells = <2>; 122*4882a593Smuzhiyun gpio-controller; 123*4882a593Smuzhiyun interrupt-controller; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun sdio1: sdio@3f180000 { 127*4882a593Smuzhiyun compatible = "brcm,kona-sdhci"; 128*4882a593Smuzhiyun reg = <0x3f180000 0x801c>; 129*4882a593Smuzhiyun interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 130*4882a593Smuzhiyun clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>; 131*4882a593Smuzhiyun status = "disabled"; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun sdio2: sdio@3f190000 { 135*4882a593Smuzhiyun compatible = "brcm,kona-sdhci"; 136*4882a593Smuzhiyun reg = <0x3f190000 0x801c>; 137*4882a593Smuzhiyun interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 138*4882a593Smuzhiyun clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>; 139*4882a593Smuzhiyun status = "disabled"; 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun sdio3: sdio@3f1a0000 { 143*4882a593Smuzhiyun compatible = "brcm,kona-sdhci"; 144*4882a593Smuzhiyun reg = <0x3f1a0000 0x801c>; 145*4882a593Smuzhiyun interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 146*4882a593Smuzhiyun clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>; 147*4882a593Smuzhiyun status = "disabled"; 148*4882a593Smuzhiyun }; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun sdio4: sdio@3f1b0000 { 151*4882a593Smuzhiyun compatible = "brcm,kona-sdhci"; 152*4882a593Smuzhiyun reg = <0x3f1b0000 0x801c>; 153*4882a593Smuzhiyun interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 154*4882a593Smuzhiyun clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>; 155*4882a593Smuzhiyun status = "disabled"; 156*4882a593Smuzhiyun }; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun i2c@3e016000 { 159*4882a593Smuzhiyun compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; 160*4882a593Smuzhiyun reg = <0x3e016000 0x70>; 161*4882a593Smuzhiyun interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 162*4882a593Smuzhiyun #address-cells = <1>; 163*4882a593Smuzhiyun #size-cells = <0>; 164*4882a593Smuzhiyun clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>; 165*4882a593Smuzhiyun status = "disabled"; 166*4882a593Smuzhiyun }; 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun i2c@3e017000 { 169*4882a593Smuzhiyun compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; 170*4882a593Smuzhiyun reg = <0x3e017000 0x70>; 171*4882a593Smuzhiyun interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 172*4882a593Smuzhiyun #address-cells = <1>; 173*4882a593Smuzhiyun #size-cells = <0>; 174*4882a593Smuzhiyun clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>; 175*4882a593Smuzhiyun status = "disabled"; 176*4882a593Smuzhiyun }; 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun i2c@3e018000 { 179*4882a593Smuzhiyun compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; 180*4882a593Smuzhiyun reg = <0x3e018000 0x70>; 181*4882a593Smuzhiyun interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 182*4882a593Smuzhiyun #address-cells = <1>; 183*4882a593Smuzhiyun #size-cells = <0>; 184*4882a593Smuzhiyun clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>; 185*4882a593Smuzhiyun status = "disabled"; 186*4882a593Smuzhiyun }; 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun i2c@3e01c000 { 189*4882a593Smuzhiyun compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c"; 190*4882a593Smuzhiyun reg = <0x3e01c000 0x70>; 191*4882a593Smuzhiyun interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 192*4882a593Smuzhiyun #address-cells = <1>; 193*4882a593Smuzhiyun #size-cells = <0>; 194*4882a593Smuzhiyun clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>; 195*4882a593Smuzhiyun status = "disabled"; 196*4882a593Smuzhiyun }; 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun clocks { 199*4882a593Smuzhiyun #address-cells = <1>; 200*4882a593Smuzhiyun #size-cells = <1>; 201*4882a593Smuzhiyun ranges; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun /* 204*4882a593Smuzhiyun * Fixed clocks are defined before CCUs whose 205*4882a593Smuzhiyun * clocks may depend on them. 206*4882a593Smuzhiyun */ 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun ref_32k_clk: ref_32k { 209*4882a593Smuzhiyun #clock-cells = <0>; 210*4882a593Smuzhiyun compatible = "fixed-clock"; 211*4882a593Smuzhiyun clock-frequency = <32768>; 212*4882a593Smuzhiyun }; 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun bbl_32k_clk: bbl_32k { 215*4882a593Smuzhiyun #clock-cells = <0>; 216*4882a593Smuzhiyun compatible = "fixed-clock"; 217*4882a593Smuzhiyun clock-frequency = <32768>; 218*4882a593Smuzhiyun }; 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun ref_13m_clk: ref_13m { 221*4882a593Smuzhiyun #clock-cells = <0>; 222*4882a593Smuzhiyun compatible = "fixed-clock"; 223*4882a593Smuzhiyun clock-frequency = <13000000>; 224*4882a593Smuzhiyun }; 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun var_13m_clk: var_13m { 227*4882a593Smuzhiyun #clock-cells = <0>; 228*4882a593Smuzhiyun compatible = "fixed-clock"; 229*4882a593Smuzhiyun clock-frequency = <13000000>; 230*4882a593Smuzhiyun }; 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun dft_19_5m_clk: dft_19_5m { 233*4882a593Smuzhiyun #clock-cells = <0>; 234*4882a593Smuzhiyun compatible = "fixed-clock"; 235*4882a593Smuzhiyun clock-frequency = <19500000>; 236*4882a593Smuzhiyun }; 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun ref_crystal_clk: ref_crystal { 239*4882a593Smuzhiyun #clock-cells = <0>; 240*4882a593Smuzhiyun compatible = "fixed-clock"; 241*4882a593Smuzhiyun clock-frequency = <26000000>; 242*4882a593Smuzhiyun }; 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun ref_52m_clk: ref_52m { 245*4882a593Smuzhiyun #clock-cells = <0>; 246*4882a593Smuzhiyun compatible = "fixed-clock"; 247*4882a593Smuzhiyun clock-frequency = <52000000>; 248*4882a593Smuzhiyun }; 249*4882a593Smuzhiyun 250*4882a593Smuzhiyun var_52m_clk: var_52m { 251*4882a593Smuzhiyun #clock-cells = <0>; 252*4882a593Smuzhiyun compatible = "fixed-clock"; 253*4882a593Smuzhiyun clock-frequency = <52000000>; 254*4882a593Smuzhiyun }; 255*4882a593Smuzhiyun 256*4882a593Smuzhiyun usb_otg_ahb_clk: usb_otg_ahb { 257*4882a593Smuzhiyun #clock-cells = <0>; 258*4882a593Smuzhiyun compatible = "fixed-clock"; 259*4882a593Smuzhiyun clock-frequency = <52000000>; 260*4882a593Smuzhiyun }; 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun ref_96m_clk: ref_96m { 263*4882a593Smuzhiyun #clock-cells = <0>; 264*4882a593Smuzhiyun compatible = "fixed-clock"; 265*4882a593Smuzhiyun clock-frequency = <96000000>; 266*4882a593Smuzhiyun }; 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun var_96m_clk: var_96m { 269*4882a593Smuzhiyun #clock-cells = <0>; 270*4882a593Smuzhiyun compatible = "fixed-clock"; 271*4882a593Smuzhiyun clock-frequency = <96000000>; 272*4882a593Smuzhiyun }; 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun ref_104m_clk: ref_104m { 275*4882a593Smuzhiyun #clock-cells = <0>; 276*4882a593Smuzhiyun compatible = "fixed-clock"; 277*4882a593Smuzhiyun clock-frequency = <104000000>; 278*4882a593Smuzhiyun }; 279*4882a593Smuzhiyun 280*4882a593Smuzhiyun var_104m_clk: var_104m { 281*4882a593Smuzhiyun #clock-cells = <0>; 282*4882a593Smuzhiyun compatible = "fixed-clock"; 283*4882a593Smuzhiyun clock-frequency = <104000000>; 284*4882a593Smuzhiyun }; 285*4882a593Smuzhiyun 286*4882a593Smuzhiyun ref_156m_clk: ref_156m { 287*4882a593Smuzhiyun #clock-cells = <0>; 288*4882a593Smuzhiyun compatible = "fixed-clock"; 289*4882a593Smuzhiyun clock-frequency = <156000000>; 290*4882a593Smuzhiyun }; 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun var_156m_clk: var_156m { 293*4882a593Smuzhiyun #clock-cells = <0>; 294*4882a593Smuzhiyun compatible = "fixed-clock"; 295*4882a593Smuzhiyun clock-frequency = <156000000>; 296*4882a593Smuzhiyun }; 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun root_ccu: root_ccu@35001000 { 299*4882a593Smuzhiyun compatible = BCM21664_DT_ROOT_CCU_COMPAT; 300*4882a593Smuzhiyun reg = <0x35001000 0x0f00>; 301*4882a593Smuzhiyun #clock-cells = <1>; 302*4882a593Smuzhiyun clock-output-names = "frac_1m"; 303*4882a593Smuzhiyun }; 304*4882a593Smuzhiyun 305*4882a593Smuzhiyun aon_ccu: aon_ccu@35002000 { 306*4882a593Smuzhiyun compatible = BCM21664_DT_AON_CCU_COMPAT; 307*4882a593Smuzhiyun reg = <0x35002000 0x0f00>; 308*4882a593Smuzhiyun #clock-cells = <1>; 309*4882a593Smuzhiyun clock-output-names = "hub_timer"; 310*4882a593Smuzhiyun }; 311*4882a593Smuzhiyun 312*4882a593Smuzhiyun master_ccu: master_ccu@3f001000 { 313*4882a593Smuzhiyun compatible = BCM21664_DT_MASTER_CCU_COMPAT; 314*4882a593Smuzhiyun reg = <0x3f001000 0x0f00>; 315*4882a593Smuzhiyun #clock-cells = <1>; 316*4882a593Smuzhiyun clock-output-names = "sdio1", 317*4882a593Smuzhiyun "sdio2", 318*4882a593Smuzhiyun "sdio3", 319*4882a593Smuzhiyun "sdio4", 320*4882a593Smuzhiyun "sdio1_sleep", 321*4882a593Smuzhiyun "sdio2_sleep", 322*4882a593Smuzhiyun "sdio3_sleep", 323*4882a593Smuzhiyun "sdio4_sleep"; 324*4882a593Smuzhiyun }; 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun slave_ccu: slave_ccu@3e011000 { 327*4882a593Smuzhiyun compatible = BCM21664_DT_SLAVE_CCU_COMPAT; 328*4882a593Smuzhiyun reg = <0x3e011000 0x0f00>; 329*4882a593Smuzhiyun #clock-cells = <1>; 330*4882a593Smuzhiyun clock-output-names = "uartb", 331*4882a593Smuzhiyun "uartb2", 332*4882a593Smuzhiyun "uartb3", 333*4882a593Smuzhiyun "bsc1", 334*4882a593Smuzhiyun "bsc2", 335*4882a593Smuzhiyun "bsc3", 336*4882a593Smuzhiyun "bsc4"; 337*4882a593Smuzhiyun }; 338*4882a593Smuzhiyun }; 339*4882a593Smuzhiyun 340*4882a593Smuzhiyun usbotg: usb@3f120000 { 341*4882a593Smuzhiyun compatible = "snps,dwc2"; 342*4882a593Smuzhiyun reg = <0x3f120000 0x10000>; 343*4882a593Smuzhiyun interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 344*4882a593Smuzhiyun clocks = <&usb_otg_ahb_clk>; 345*4882a593Smuzhiyun clock-names = "otg"; 346*4882a593Smuzhiyun phys = <&usbphy>; 347*4882a593Smuzhiyun phy-names = "usb2-phy"; 348*4882a593Smuzhiyun status = "disabled"; 349*4882a593Smuzhiyun }; 350*4882a593Smuzhiyun 351*4882a593Smuzhiyun usbphy: usb-phy@3f130000 { 352*4882a593Smuzhiyun compatible = "brcm,kona-usb2-phy"; 353*4882a593Smuzhiyun reg = <0x3f130000 0x28>; 354*4882a593Smuzhiyun #phy-cells = <0>; 355*4882a593Smuzhiyun status = "disabled"; 356*4882a593Smuzhiyun }; 357*4882a593Smuzhiyun}; 358