1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * at91sam9rl.dtsi - Device Tree Include file for AT91SAM9RL family SoC 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2014 Microchip 6*4882a593Smuzhiyun * Alexandre Belloni <alexandre.belloni@free-electrons.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include <dt-bindings/pinctrl/at91.h> 10*4882a593Smuzhiyun#include <dt-bindings/clock/at91.h> 11*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 12*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 13*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun/ { 16*4882a593Smuzhiyun #address-cells = <1>; 17*4882a593Smuzhiyun #size-cells = <1>; 18*4882a593Smuzhiyun model = "Atmel AT91SAM9RL family SoC"; 19*4882a593Smuzhiyun compatible = "atmel,at91sam9rl", "atmel,at91sam9"; 20*4882a593Smuzhiyun interrupt-parent = <&aic>; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun aliases { 23*4882a593Smuzhiyun serial0 = &dbgu; 24*4882a593Smuzhiyun serial1 = &usart0; 25*4882a593Smuzhiyun serial2 = &usart1; 26*4882a593Smuzhiyun serial3 = &usart2; 27*4882a593Smuzhiyun serial4 = &usart3; 28*4882a593Smuzhiyun gpio0 = &pioA; 29*4882a593Smuzhiyun gpio1 = &pioB; 30*4882a593Smuzhiyun gpio2 = &pioC; 31*4882a593Smuzhiyun gpio3 = &pioD; 32*4882a593Smuzhiyun tcb0 = &tcb0; 33*4882a593Smuzhiyun i2c0 = &i2c0; 34*4882a593Smuzhiyun i2c1 = &i2c1; 35*4882a593Smuzhiyun ssc0 = &ssc0; 36*4882a593Smuzhiyun ssc1 = &ssc1; 37*4882a593Smuzhiyun pwm0 = &pwm0; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun cpus { 41*4882a593Smuzhiyun #address-cells = <1>; 42*4882a593Smuzhiyun #size-cells = <0>; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun cpu@0 { 45*4882a593Smuzhiyun compatible = "arm,arm926ej-s"; 46*4882a593Smuzhiyun device_type = "cpu"; 47*4882a593Smuzhiyun reg = <0>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun memory@20000000 { 52*4882a593Smuzhiyun device_type = "memory"; 53*4882a593Smuzhiyun reg = <0x20000000 0x04000000>; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun clocks { 57*4882a593Smuzhiyun slow_xtal: slow_xtal { 58*4882a593Smuzhiyun compatible = "fixed-clock"; 59*4882a593Smuzhiyun #clock-cells = <0>; 60*4882a593Smuzhiyun clock-frequency = <0>; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun main_xtal: main_xtal { 64*4882a593Smuzhiyun compatible = "fixed-clock"; 65*4882a593Smuzhiyun #clock-cells = <0>; 66*4882a593Smuzhiyun clock-frequency = <0>; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun adc_op_clk: adc_op_clk{ 70*4882a593Smuzhiyun compatible = "fixed-clock"; 71*4882a593Smuzhiyun #clock-cells = <0>; 72*4882a593Smuzhiyun clock-frequency = <1000000>; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun sram: sram@300000 { 77*4882a593Smuzhiyun compatible = "mmio-sram"; 78*4882a593Smuzhiyun reg = <0x00300000 0x10000>; 79*4882a593Smuzhiyun #address-cells = <1>; 80*4882a593Smuzhiyun #size-cells = <1>; 81*4882a593Smuzhiyun ranges = <0 0x00300000 0x10000>; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun ahb { 85*4882a593Smuzhiyun compatible = "simple-bus"; 86*4882a593Smuzhiyun #address-cells = <1>; 87*4882a593Smuzhiyun #size-cells = <1>; 88*4882a593Smuzhiyun ranges; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun fb0: fb@500000 { 91*4882a593Smuzhiyun compatible = "atmel,at91sam9rl-lcdc"; 92*4882a593Smuzhiyun reg = <0x00500000 0x1000>; 93*4882a593Smuzhiyun interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>; 94*4882a593Smuzhiyun pinctrl-names = "default"; 95*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_fb>; 96*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_PERIPHERAL 23>; 97*4882a593Smuzhiyun clock-names = "hclk", "lcdc_clk"; 98*4882a593Smuzhiyun status = "disabled"; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun ebi: ebi@10000000 { 102*4882a593Smuzhiyun compatible = "atmel,at91sam9rl-ebi"; 103*4882a593Smuzhiyun #address-cells = <2>; 104*4882a593Smuzhiyun #size-cells = <1>; 105*4882a593Smuzhiyun atmel,smc = <&smc>; 106*4882a593Smuzhiyun atmel,matrix = <&matrix>; 107*4882a593Smuzhiyun reg = <0x10000000 0x80000000>; 108*4882a593Smuzhiyun ranges = <0x0 0x0 0x10000000 0x10000000 109*4882a593Smuzhiyun 0x1 0x0 0x20000000 0x10000000 110*4882a593Smuzhiyun 0x2 0x0 0x30000000 0x10000000 111*4882a593Smuzhiyun 0x3 0x0 0x40000000 0x10000000 112*4882a593Smuzhiyun 0x4 0x0 0x50000000 0x10000000 113*4882a593Smuzhiyun 0x5 0x0 0x60000000 0x10000000>; 114*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 115*4882a593Smuzhiyun status = "disabled"; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun nand_controller: nand-controller { 118*4882a593Smuzhiyun compatible = "atmel,at91sam9g45-nand-controller"; 119*4882a593Smuzhiyun #address-cells = <2>; 120*4882a593Smuzhiyun #size-cells = <1>; 121*4882a593Smuzhiyun ranges; 122*4882a593Smuzhiyun status = "disabled"; 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun apb { 127*4882a593Smuzhiyun compatible = "simple-bus"; 128*4882a593Smuzhiyun #address-cells = <1>; 129*4882a593Smuzhiyun #size-cells = <1>; 130*4882a593Smuzhiyun ranges; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun tcb0: timer@fffa0000 { 133*4882a593Smuzhiyun compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; 134*4882a593Smuzhiyun #address-cells = <1>; 135*4882a593Smuzhiyun #size-cells = <0>; 136*4882a593Smuzhiyun reg = <0xfffa0000 0x100>; 137*4882a593Smuzhiyun interrupts = <16 IRQ_TYPE_LEVEL_HIGH 0>, 138*4882a593Smuzhiyun <17 IRQ_TYPE_LEVEL_HIGH 0>, 139*4882a593Smuzhiyun <18 IRQ_TYPE_LEVEL_HIGH 0>; 140*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 16>, <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&clk32k>; 141*4882a593Smuzhiyun clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; 142*4882a593Smuzhiyun }; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun mmc0: mmc@fffa4000 { 145*4882a593Smuzhiyun compatible = "atmel,hsmci"; 146*4882a593Smuzhiyun reg = <0xfffa4000 0x600>; 147*4882a593Smuzhiyun interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; 148*4882a593Smuzhiyun #address-cells = <1>; 149*4882a593Smuzhiyun #size-cells = <0>; 150*4882a593Smuzhiyun pinctrl-names = "default"; 151*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 152*4882a593Smuzhiyun clock-names = "mci_clk"; 153*4882a593Smuzhiyun status = "disabled"; 154*4882a593Smuzhiyun }; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun i2c0: i2c@fffa8000 { 157*4882a593Smuzhiyun compatible = "atmel,at91sam9260-i2c"; 158*4882a593Smuzhiyun reg = <0xfffa8000 0x100>; 159*4882a593Smuzhiyun interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; 160*4882a593Smuzhiyun #address-cells = <1>; 161*4882a593Smuzhiyun #size-cells = <0>; 162*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 163*4882a593Smuzhiyun status = "disabled"; 164*4882a593Smuzhiyun }; 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun i2c1: i2c@fffac000 { 167*4882a593Smuzhiyun compatible = "atmel,at91sam9260-i2c"; 168*4882a593Smuzhiyun reg = <0xfffac000 0x100>; 169*4882a593Smuzhiyun interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; 170*4882a593Smuzhiyun #address-cells = <1>; 171*4882a593Smuzhiyun #size-cells = <0>; 172*4882a593Smuzhiyun status = "disabled"; 173*4882a593Smuzhiyun }; 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun usart0: serial@fffb0000 { 176*4882a593Smuzhiyun compatible = "atmel,at91sam9260-usart"; 177*4882a593Smuzhiyun reg = <0xfffb0000 0x200>; 178*4882a593Smuzhiyun interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; 179*4882a593Smuzhiyun atmel,use-dma-rx; 180*4882a593Smuzhiyun atmel,use-dma-tx; 181*4882a593Smuzhiyun pinctrl-names = "default"; 182*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usart0>; 183*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 184*4882a593Smuzhiyun clock-names = "usart"; 185*4882a593Smuzhiyun status = "disabled"; 186*4882a593Smuzhiyun }; 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun usart1: serial@fffb4000 { 189*4882a593Smuzhiyun compatible = "atmel,at91sam9260-usart"; 190*4882a593Smuzhiyun reg = <0xfffb4000 0x200>; 191*4882a593Smuzhiyun interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; 192*4882a593Smuzhiyun atmel,use-dma-rx; 193*4882a593Smuzhiyun atmel,use-dma-tx; 194*4882a593Smuzhiyun pinctrl-names = "default"; 195*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usart1>; 196*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 197*4882a593Smuzhiyun clock-names = "usart"; 198*4882a593Smuzhiyun status = "disabled"; 199*4882a593Smuzhiyun }; 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun usart2: serial@fffb8000 { 202*4882a593Smuzhiyun compatible = "atmel,at91sam9260-usart"; 203*4882a593Smuzhiyun reg = <0xfffb8000 0x200>; 204*4882a593Smuzhiyun interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; 205*4882a593Smuzhiyun atmel,use-dma-rx; 206*4882a593Smuzhiyun atmel,use-dma-tx; 207*4882a593Smuzhiyun pinctrl-names = "default"; 208*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usart2>; 209*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 210*4882a593Smuzhiyun clock-names = "usart"; 211*4882a593Smuzhiyun status = "disabled"; 212*4882a593Smuzhiyun }; 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun usart3: serial@fffbc000 { 215*4882a593Smuzhiyun compatible = "atmel,at91sam9260-usart"; 216*4882a593Smuzhiyun reg = <0xfffbc000 0x200>; 217*4882a593Smuzhiyun interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>; 218*4882a593Smuzhiyun atmel,use-dma-rx; 219*4882a593Smuzhiyun atmel,use-dma-tx; 220*4882a593Smuzhiyun pinctrl-names = "default"; 221*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usart3>; 222*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 223*4882a593Smuzhiyun clock-names = "usart"; 224*4882a593Smuzhiyun status = "disabled"; 225*4882a593Smuzhiyun }; 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun ssc0: ssc@fffc0000 { 228*4882a593Smuzhiyun compatible = "atmel,at91sam9rl-ssc"; 229*4882a593Smuzhiyun reg = <0xfffc0000 0x4000>; 230*4882a593Smuzhiyun interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; 231*4882a593Smuzhiyun pinctrl-names = "default"; 232*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; 233*4882a593Smuzhiyun status = "disabled"; 234*4882a593Smuzhiyun }; 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun ssc1: ssc@fffc4000 { 237*4882a593Smuzhiyun compatible = "atmel,at91sam9rl-ssc"; 238*4882a593Smuzhiyun reg = <0xfffc4000 0x4000>; 239*4882a593Smuzhiyun interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; 240*4882a593Smuzhiyun pinctrl-names = "default"; 241*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; 242*4882a593Smuzhiyun status = "disabled"; 243*4882a593Smuzhiyun }; 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun pwm0: pwm@fffc8000 { 246*4882a593Smuzhiyun compatible = "atmel,at91sam9rl-pwm"; 247*4882a593Smuzhiyun reg = <0xfffc8000 0x300>; 248*4882a593Smuzhiyun interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; 249*4882a593Smuzhiyun #pwm-cells = <3>; 250*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 251*4882a593Smuzhiyun clock-names = "pwm_clk"; 252*4882a593Smuzhiyun status = "disabled"; 253*4882a593Smuzhiyun }; 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun spi0: spi@fffcc000 { 256*4882a593Smuzhiyun #address-cells = <1>; 257*4882a593Smuzhiyun #size-cells = <0>; 258*4882a593Smuzhiyun compatible = "atmel,at91rm9200-spi"; 259*4882a593Smuzhiyun reg = <0xfffcc000 0x200>; 260*4882a593Smuzhiyun interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; 261*4882a593Smuzhiyun pinctrl-names = "default"; 262*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_spi0>; 263*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 264*4882a593Smuzhiyun clock-names = "spi_clk"; 265*4882a593Smuzhiyun status = "disabled"; 266*4882a593Smuzhiyun }; 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun adc0: adc@fffd0000 { 269*4882a593Smuzhiyun #address-cells = <1>; 270*4882a593Smuzhiyun #size-cells = <0>; 271*4882a593Smuzhiyun compatible = "atmel,at91sam9rl-adc"; 272*4882a593Smuzhiyun reg = <0xfffd0000 0x100>; 273*4882a593Smuzhiyun interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; 274*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&adc_op_clk>; 275*4882a593Smuzhiyun clock-names = "adc_clk", "adc_op_clk"; 276*4882a593Smuzhiyun atmel,adc-use-external-triggers; 277*4882a593Smuzhiyun atmel,adc-channels-used = <0x3f>; 278*4882a593Smuzhiyun atmel,adc-vref = <3300>; 279*4882a593Smuzhiyun atmel,adc-startup-time = <40>; 280*4882a593Smuzhiyun atmel,adc-res = <8 10>; 281*4882a593Smuzhiyun atmel,adc-res-names = "lowres", "highres"; 282*4882a593Smuzhiyun atmel,adc-use-res = "highres"; 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun trigger0 { 285*4882a593Smuzhiyun trigger-name = "external-rising"; 286*4882a593Smuzhiyun trigger-value = <0x1>; 287*4882a593Smuzhiyun trigger-external; 288*4882a593Smuzhiyun }; 289*4882a593Smuzhiyun 290*4882a593Smuzhiyun trigger1 { 291*4882a593Smuzhiyun trigger-name = "external-falling"; 292*4882a593Smuzhiyun trigger-value = <0x2>; 293*4882a593Smuzhiyun trigger-external; 294*4882a593Smuzhiyun }; 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun trigger2 { 297*4882a593Smuzhiyun trigger-name = "external-any"; 298*4882a593Smuzhiyun trigger-value = <0x3>; 299*4882a593Smuzhiyun trigger-external; 300*4882a593Smuzhiyun }; 301*4882a593Smuzhiyun 302*4882a593Smuzhiyun trigger3 { 303*4882a593Smuzhiyun trigger-name = "continuous"; 304*4882a593Smuzhiyun trigger-value = <0x6>; 305*4882a593Smuzhiyun }; 306*4882a593Smuzhiyun }; 307*4882a593Smuzhiyun 308*4882a593Smuzhiyun usb0: gadget@fffd4000 { 309*4882a593Smuzhiyun compatible = "atmel,at91sam9rl-udc"; 310*4882a593Smuzhiyun reg = <0x00600000 0x100000>, 311*4882a593Smuzhiyun <0xfffd4000 0x4000>; 312*4882a593Smuzhiyun interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; 313*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_CORE PMC_UTMI>; 314*4882a593Smuzhiyun clock-names = "pclk", "hclk"; 315*4882a593Smuzhiyun status = "disabled"; 316*4882a593Smuzhiyun }; 317*4882a593Smuzhiyun 318*4882a593Smuzhiyun dma0: dma-controller@ffffe600 { 319*4882a593Smuzhiyun compatible = "atmel,at91sam9rl-dma"; 320*4882a593Smuzhiyun reg = <0xffffe600 0x200>; 321*4882a593Smuzhiyun interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; 322*4882a593Smuzhiyun #dma-cells = <2>; 323*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 324*4882a593Smuzhiyun clock-names = "dma_clk"; 325*4882a593Smuzhiyun }; 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun ramc0: ramc@ffffea00 { 328*4882a593Smuzhiyun compatible = "atmel,at91sam9260-sdramc"; 329*4882a593Smuzhiyun reg = <0xffffea00 0x200>; 330*4882a593Smuzhiyun }; 331*4882a593Smuzhiyun 332*4882a593Smuzhiyun smc: smc@ffffec00 { 333*4882a593Smuzhiyun compatible = "atmel,at91sam9260-smc", "syscon"; 334*4882a593Smuzhiyun reg = <0xffffec00 0x200>; 335*4882a593Smuzhiyun }; 336*4882a593Smuzhiyun 337*4882a593Smuzhiyun matrix: matrix@ffffee00 { 338*4882a593Smuzhiyun compatible = "atmel,at91sam9rl-matrix", "syscon"; 339*4882a593Smuzhiyun reg = <0xffffee00 0x200>; 340*4882a593Smuzhiyun }; 341*4882a593Smuzhiyun 342*4882a593Smuzhiyun aic: interrupt-controller@fffff000 { 343*4882a593Smuzhiyun #interrupt-cells = <3>; 344*4882a593Smuzhiyun compatible = "atmel,at91rm9200-aic"; 345*4882a593Smuzhiyun interrupt-controller; 346*4882a593Smuzhiyun reg = <0xfffff000 0x200>; 347*4882a593Smuzhiyun atmel,external-irqs = <31>; 348*4882a593Smuzhiyun }; 349*4882a593Smuzhiyun 350*4882a593Smuzhiyun dbgu: serial@fffff200 { 351*4882a593Smuzhiyun compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 352*4882a593Smuzhiyun reg = <0xfffff200 0x200>; 353*4882a593Smuzhiyun interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 354*4882a593Smuzhiyun pinctrl-names = "default"; 355*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_dbgu>; 356*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 357*4882a593Smuzhiyun clock-names = "usart"; 358*4882a593Smuzhiyun status = "disabled"; 359*4882a593Smuzhiyun }; 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun pinctrl@fffff400 { 362*4882a593Smuzhiyun #address-cells = <1>; 363*4882a593Smuzhiyun #size-cells = <1>; 364*4882a593Smuzhiyun compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; 365*4882a593Smuzhiyun ranges = <0xfffff400 0xfffff400 0x800>; 366*4882a593Smuzhiyun 367*4882a593Smuzhiyun atmel,mux-mask = 368*4882a593Smuzhiyun /* A B */ 369*4882a593Smuzhiyun <0xffffffff 0xe05c6738>, /* pioA */ 370*4882a593Smuzhiyun <0xffffffff 0x0000c780>, /* pioB */ 371*4882a593Smuzhiyun <0xffffffff 0xe3ffff0e>, /* pioC */ 372*4882a593Smuzhiyun <0x003fffff 0x0001ff3c>; /* pioD */ 373*4882a593Smuzhiyun 374*4882a593Smuzhiyun /* shared pinctrl settings */ 375*4882a593Smuzhiyun adc0 { 376*4882a593Smuzhiyun pinctrl_adc0_ts: adc0_ts-0 { 377*4882a593Smuzhiyun atmel,pins = 378*4882a593Smuzhiyun <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE>, 379*4882a593Smuzhiyun <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>, 380*4882a593Smuzhiyun <AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>, 381*4882a593Smuzhiyun <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; 382*4882a593Smuzhiyun }; 383*4882a593Smuzhiyun 384*4882a593Smuzhiyun pinctrl_adc0_ad0: adc0_ad0-0 { 385*4882a593Smuzhiyun atmel,pins = <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; 386*4882a593Smuzhiyun }; 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun pinctrl_adc0_ad1: adc0_ad1-0 { 389*4882a593Smuzhiyun atmel,pins = <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; 390*4882a593Smuzhiyun }; 391*4882a593Smuzhiyun 392*4882a593Smuzhiyun pinctrl_adc0_ad2: adc0_ad2-0 { 393*4882a593Smuzhiyun atmel,pins = <AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; 394*4882a593Smuzhiyun }; 395*4882a593Smuzhiyun 396*4882a593Smuzhiyun pinctrl_adc0_ad3: adc0_ad3-0 { 397*4882a593Smuzhiyun atmel,pins = <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; 398*4882a593Smuzhiyun }; 399*4882a593Smuzhiyun 400*4882a593Smuzhiyun pinctrl_adc0_ad4: adc0_ad4-0 { 401*4882a593Smuzhiyun atmel,pins = <AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; 402*4882a593Smuzhiyun }; 403*4882a593Smuzhiyun 404*4882a593Smuzhiyun pinctrl_adc0_ad5: adc0_ad5-0 { 405*4882a593Smuzhiyun atmel,pins = <AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; 406*4882a593Smuzhiyun }; 407*4882a593Smuzhiyun 408*4882a593Smuzhiyun pinctrl_adc0_adtrg: adc0_adtrg-0 { 409*4882a593Smuzhiyun atmel,pins = <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; 410*4882a593Smuzhiyun }; 411*4882a593Smuzhiyun }; 412*4882a593Smuzhiyun 413*4882a593Smuzhiyun dbgu { 414*4882a593Smuzhiyun pinctrl_dbgu: dbgu-0 { 415*4882a593Smuzhiyun atmel,pins = 416*4882a593Smuzhiyun <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>, 417*4882a593Smuzhiyun <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; 418*4882a593Smuzhiyun }; 419*4882a593Smuzhiyun }; 420*4882a593Smuzhiyun 421*4882a593Smuzhiyun ebi { 422*4882a593Smuzhiyun pinctrl_ebi_addr_nand: ebi-addr-0 { 423*4882a593Smuzhiyun atmel,pins = 424*4882a593Smuzhiyun <AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>, 425*4882a593Smuzhiyun <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; 426*4882a593Smuzhiyun }; 427*4882a593Smuzhiyun }; 428*4882a593Smuzhiyun 429*4882a593Smuzhiyun fb { 430*4882a593Smuzhiyun pinctrl_fb: fb-0 { 431*4882a593Smuzhiyun atmel,pins = 432*4882a593Smuzhiyun <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>, 433*4882a593Smuzhiyun <AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE>, 434*4882a593Smuzhiyun <AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE>, 435*4882a593Smuzhiyun <AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE>, 436*4882a593Smuzhiyun <AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE>, 437*4882a593Smuzhiyun <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>, 438*4882a593Smuzhiyun <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>, 439*4882a593Smuzhiyun <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>, 440*4882a593Smuzhiyun <AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_NONE>, 441*4882a593Smuzhiyun <AT91_PIOC 13 AT91_PERIPH_B AT91_PINCTRL_NONE>, 442*4882a593Smuzhiyun <AT91_PIOC 15 AT91_PERIPH_B AT91_PINCTRL_NONE>, 443*4882a593Smuzhiyun <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE>, 444*4882a593Smuzhiyun <AT91_PIOC 17 AT91_PERIPH_B AT91_PINCTRL_NONE>, 445*4882a593Smuzhiyun <AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE>, 446*4882a593Smuzhiyun <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE>, 447*4882a593Smuzhiyun <AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE>, 448*4882a593Smuzhiyun <AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>, 449*4882a593Smuzhiyun <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>, 450*4882a593Smuzhiyun <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>, 451*4882a593Smuzhiyun <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>, 452*4882a593Smuzhiyun <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; 453*4882a593Smuzhiyun }; 454*4882a593Smuzhiyun }; 455*4882a593Smuzhiyun 456*4882a593Smuzhiyun i2c_gpio0 { 457*4882a593Smuzhiyun pinctrl_i2c_gpio0: i2c_gpio0-0 { 458*4882a593Smuzhiyun atmel,pins = 459*4882a593Smuzhiyun <AT91_PIOA 23 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>, 460*4882a593Smuzhiyun <AT91_PIOA 24 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; 461*4882a593Smuzhiyun }; 462*4882a593Smuzhiyun }; 463*4882a593Smuzhiyun 464*4882a593Smuzhiyun i2c_gpio1 { 465*4882a593Smuzhiyun pinctrl_i2c_gpio1: i2c_gpio1-0 { 466*4882a593Smuzhiyun atmel,pins = 467*4882a593Smuzhiyun <AT91_PIOD 10 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>, 468*4882a593Smuzhiyun <AT91_PIOD 11 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; 469*4882a593Smuzhiyun }; 470*4882a593Smuzhiyun }; 471*4882a593Smuzhiyun 472*4882a593Smuzhiyun mmc0 { 473*4882a593Smuzhiyun pinctrl_mmc0_clk: mmc0_clk-0 { 474*4882a593Smuzhiyun atmel,pins = 475*4882a593Smuzhiyun <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; 476*4882a593Smuzhiyun }; 477*4882a593Smuzhiyun 478*4882a593Smuzhiyun pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { 479*4882a593Smuzhiyun atmel,pins = 480*4882a593Smuzhiyun <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>, 481*4882a593Smuzhiyun <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; 482*4882a593Smuzhiyun }; 483*4882a593Smuzhiyun 484*4882a593Smuzhiyun pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { 485*4882a593Smuzhiyun atmel,pins = 486*4882a593Smuzhiyun <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>, 487*4882a593Smuzhiyun <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>, 488*4882a593Smuzhiyun <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; 489*4882a593Smuzhiyun }; 490*4882a593Smuzhiyun }; 491*4882a593Smuzhiyun 492*4882a593Smuzhiyun nand { 493*4882a593Smuzhiyun pinctrl_nand_rb: nand-rb-0 { 494*4882a593Smuzhiyun atmel,pins = 495*4882a593Smuzhiyun <AT91_PIOD 17 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; 496*4882a593Smuzhiyun }; 497*4882a593Smuzhiyun 498*4882a593Smuzhiyun pinctrl_nand_cs: nand-cs-0 { 499*4882a593Smuzhiyun atmel,pins = 500*4882a593Smuzhiyun <AT91_PIOB 6 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; 501*4882a593Smuzhiyun }; 502*4882a593Smuzhiyun 503*4882a593Smuzhiyun pinctrl_nand_oe_we: nand-oe-we-0 { 504*4882a593Smuzhiyun atmel,pins = 505*4882a593Smuzhiyun <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE>, 506*4882a593Smuzhiyun <AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; 507*4882a593Smuzhiyun }; 508*4882a593Smuzhiyun }; 509*4882a593Smuzhiyun 510*4882a593Smuzhiyun pwm0 { 511*4882a593Smuzhiyun pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 { 512*4882a593Smuzhiyun atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; 513*4882a593Smuzhiyun }; 514*4882a593Smuzhiyun 515*4882a593Smuzhiyun pinctrl_pwm0_pwm0_1: pwm0_pwm0-1 { 516*4882a593Smuzhiyun atmel,pins = <AT91_PIOC 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; 517*4882a593Smuzhiyun }; 518*4882a593Smuzhiyun 519*4882a593Smuzhiyun pinctrl_pwm0_pwm0_2: pwm0_pwm0-2 { 520*4882a593Smuzhiyun atmel,pins = <AT91_PIOD 14 AT91_PERIPH_B AT91_PINCTRL_NONE>; 521*4882a593Smuzhiyun }; 522*4882a593Smuzhiyun 523*4882a593Smuzhiyun pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 { 524*4882a593Smuzhiyun atmel,pins = <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; 525*4882a593Smuzhiyun }; 526*4882a593Smuzhiyun 527*4882a593Smuzhiyun pinctrl_pwm0_pwm1_1: pwm0_pwm1-1 { 528*4882a593Smuzhiyun atmel,pins = <AT91_PIOC 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; 529*4882a593Smuzhiyun }; 530*4882a593Smuzhiyun 531*4882a593Smuzhiyun pinctrl_pwm0_pwm1_2: pwm0_pwm1-2 { 532*4882a593Smuzhiyun atmel,pins = <AT91_PIOD 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; 533*4882a593Smuzhiyun }; 534*4882a593Smuzhiyun 535*4882a593Smuzhiyun pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 { 536*4882a593Smuzhiyun atmel,pins = <AT91_PIOD 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; 537*4882a593Smuzhiyun }; 538*4882a593Smuzhiyun 539*4882a593Smuzhiyun pinctrl_pwm0_pwm2_1: pwm0_pwm2-1 { 540*4882a593Smuzhiyun atmel,pins = <AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; 541*4882a593Smuzhiyun }; 542*4882a593Smuzhiyun 543*4882a593Smuzhiyun pinctrl_pwm0_pwm2_2: pwm0_pwm2-2 { 544*4882a593Smuzhiyun atmel,pins = <AT91_PIOD 16 AT91_PERIPH_B AT91_PINCTRL_NONE>; 545*4882a593Smuzhiyun }; 546*4882a593Smuzhiyun 547*4882a593Smuzhiyun pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 { 548*4882a593Smuzhiyun atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; 549*4882a593Smuzhiyun }; 550*4882a593Smuzhiyun 551*4882a593Smuzhiyun pinctrl_pwm0_pwm3_1: pwm0_pwm3-1 { 552*4882a593Smuzhiyun atmel,pins = <AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; 553*4882a593Smuzhiyun }; 554*4882a593Smuzhiyun }; 555*4882a593Smuzhiyun 556*4882a593Smuzhiyun spi0 { 557*4882a593Smuzhiyun pinctrl_spi0: spi0-0 { 558*4882a593Smuzhiyun atmel,pins = 559*4882a593Smuzhiyun <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>, 560*4882a593Smuzhiyun <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>, 561*4882a593Smuzhiyun <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; 562*4882a593Smuzhiyun }; 563*4882a593Smuzhiyun }; 564*4882a593Smuzhiyun 565*4882a593Smuzhiyun ssc0 { 566*4882a593Smuzhiyun pinctrl_ssc0_tx: ssc0_tx-0 { 567*4882a593Smuzhiyun atmel,pins = 568*4882a593Smuzhiyun <AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>, 569*4882a593Smuzhiyun <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE>, 570*4882a593Smuzhiyun <AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; 571*4882a593Smuzhiyun }; 572*4882a593Smuzhiyun 573*4882a593Smuzhiyun pinctrl_ssc0_rx: ssc0_rx-0 { 574*4882a593Smuzhiyun atmel,pins = 575*4882a593Smuzhiyun <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE>, 576*4882a593Smuzhiyun <AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE>, 577*4882a593Smuzhiyun <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; 578*4882a593Smuzhiyun }; 579*4882a593Smuzhiyun }; 580*4882a593Smuzhiyun 581*4882a593Smuzhiyun ssc1 { 582*4882a593Smuzhiyun pinctrl_ssc1_tx: ssc1_tx-0 { 583*4882a593Smuzhiyun atmel,pins = 584*4882a593Smuzhiyun <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>, 585*4882a593Smuzhiyun <AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>, 586*4882a593Smuzhiyun <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; 587*4882a593Smuzhiyun }; 588*4882a593Smuzhiyun 589*4882a593Smuzhiyun pinctrl_ssc1_rx: ssc1_rx-0 { 590*4882a593Smuzhiyun atmel,pins = 591*4882a593Smuzhiyun <AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE>, 592*4882a593Smuzhiyun <AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE>, 593*4882a593Smuzhiyun <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE>; 594*4882a593Smuzhiyun }; 595*4882a593Smuzhiyun }; 596*4882a593Smuzhiyun 597*4882a593Smuzhiyun tcb0 { 598*4882a593Smuzhiyun pinctrl_tcb0_tclk0: tcb0_tclk0-0 { 599*4882a593Smuzhiyun atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; 600*4882a593Smuzhiyun }; 601*4882a593Smuzhiyun 602*4882a593Smuzhiyun pinctrl_tcb0_tclk1: tcb0_tclk1-0 { 603*4882a593Smuzhiyun atmel,pins = <AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; 604*4882a593Smuzhiyun }; 605*4882a593Smuzhiyun 606*4882a593Smuzhiyun pinctrl_tcb0_tclk2: tcb0_tclk2-0 { 607*4882a593Smuzhiyun atmel,pins = <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; 608*4882a593Smuzhiyun }; 609*4882a593Smuzhiyun 610*4882a593Smuzhiyun pinctrl_tcb0_tioa0: tcb0_tioa0-0 { 611*4882a593Smuzhiyun atmel,pins = <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE>; 612*4882a593Smuzhiyun }; 613*4882a593Smuzhiyun 614*4882a593Smuzhiyun pinctrl_tcb0_tioa1: tcb0_tioa1-0 { 615*4882a593Smuzhiyun atmel,pins = <AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; 616*4882a593Smuzhiyun }; 617*4882a593Smuzhiyun 618*4882a593Smuzhiyun pinctrl_tcb0_tioa2: tcb0_tioa2-0 { 619*4882a593Smuzhiyun atmel,pins = <AT91_PIOD 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; 620*4882a593Smuzhiyun }; 621*4882a593Smuzhiyun 622*4882a593Smuzhiyun pinctrl_tcb0_tiob0: tcb0_tiob0-0 { 623*4882a593Smuzhiyun atmel,pins = <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; 624*4882a593Smuzhiyun }; 625*4882a593Smuzhiyun 626*4882a593Smuzhiyun pinctrl_tcb0_tiob1: tcb0_tiob1-0 { 627*4882a593Smuzhiyun atmel,pins = <AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; 628*4882a593Smuzhiyun }; 629*4882a593Smuzhiyun 630*4882a593Smuzhiyun pinctrl_tcb0_tiob2: tcb0_tiob2-0 { 631*4882a593Smuzhiyun atmel,pins = <AT91_PIOD 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; 632*4882a593Smuzhiyun }; 633*4882a593Smuzhiyun }; 634*4882a593Smuzhiyun 635*4882a593Smuzhiyun usart0 { 636*4882a593Smuzhiyun pinctrl_usart0: usart0-0 { 637*4882a593Smuzhiyun atmel,pins = 638*4882a593Smuzhiyun <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>, 639*4882a593Smuzhiyun <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; 640*4882a593Smuzhiyun }; 641*4882a593Smuzhiyun 642*4882a593Smuzhiyun pinctrl_usart0_rts: usart0_rts-0 { 643*4882a593Smuzhiyun atmel,pins = 644*4882a593Smuzhiyun <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; 645*4882a593Smuzhiyun }; 646*4882a593Smuzhiyun 647*4882a593Smuzhiyun pinctrl_usart0_cts: usart0_cts-0 { 648*4882a593Smuzhiyun atmel,pins = 649*4882a593Smuzhiyun <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; 650*4882a593Smuzhiyun }; 651*4882a593Smuzhiyun 652*4882a593Smuzhiyun pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 { 653*4882a593Smuzhiyun atmel,pins = 654*4882a593Smuzhiyun <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE>, 655*4882a593Smuzhiyun <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; 656*4882a593Smuzhiyun }; 657*4882a593Smuzhiyun 658*4882a593Smuzhiyun pinctrl_usart0_dcd: usart0_dcd-0 { 659*4882a593Smuzhiyun atmel,pins = 660*4882a593Smuzhiyun <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; 661*4882a593Smuzhiyun }; 662*4882a593Smuzhiyun 663*4882a593Smuzhiyun pinctrl_usart0_ri: usart0_ri-0 { 664*4882a593Smuzhiyun atmel,pins = 665*4882a593Smuzhiyun <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; 666*4882a593Smuzhiyun }; 667*4882a593Smuzhiyun 668*4882a593Smuzhiyun pinctrl_usart0_sck: usart0_sck-0 { 669*4882a593Smuzhiyun atmel,pins = 670*4882a593Smuzhiyun <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; 671*4882a593Smuzhiyun }; 672*4882a593Smuzhiyun }; 673*4882a593Smuzhiyun 674*4882a593Smuzhiyun usart1 { 675*4882a593Smuzhiyun pinctrl_usart1: usart1-0 { 676*4882a593Smuzhiyun atmel,pins = 677*4882a593Smuzhiyun <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>, 678*4882a593Smuzhiyun <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; 679*4882a593Smuzhiyun }; 680*4882a593Smuzhiyun 681*4882a593Smuzhiyun pinctrl_usart1_rts: usart1_rts-0 { 682*4882a593Smuzhiyun atmel,pins = 683*4882a593Smuzhiyun <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE>; 684*4882a593Smuzhiyun }; 685*4882a593Smuzhiyun 686*4882a593Smuzhiyun pinctrl_usart1_cts: usart1_cts-0 { 687*4882a593Smuzhiyun atmel,pins = 688*4882a593Smuzhiyun <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; 689*4882a593Smuzhiyun }; 690*4882a593Smuzhiyun 691*4882a593Smuzhiyun pinctrl_usart1_sck: usart1_sck-0 { 692*4882a593Smuzhiyun atmel,pins = 693*4882a593Smuzhiyun <AT91_PIOD 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; 694*4882a593Smuzhiyun }; 695*4882a593Smuzhiyun }; 696*4882a593Smuzhiyun 697*4882a593Smuzhiyun usart2 { 698*4882a593Smuzhiyun pinctrl_usart2: usart2-0 { 699*4882a593Smuzhiyun atmel,pins = 700*4882a593Smuzhiyun <AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>, 701*4882a593Smuzhiyun <AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; 702*4882a593Smuzhiyun }; 703*4882a593Smuzhiyun 704*4882a593Smuzhiyun pinctrl_usart2_rts: usart2_rts-0 { 705*4882a593Smuzhiyun atmel,pins = 706*4882a593Smuzhiyun <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; 707*4882a593Smuzhiyun }; 708*4882a593Smuzhiyun 709*4882a593Smuzhiyun pinctrl_usart2_cts: usart2_cts-0 { 710*4882a593Smuzhiyun atmel,pins = 711*4882a593Smuzhiyun <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; 712*4882a593Smuzhiyun }; 713*4882a593Smuzhiyun 714*4882a593Smuzhiyun pinctrl_usart2_sck: usart2_sck-0 { 715*4882a593Smuzhiyun atmel,pins = 716*4882a593Smuzhiyun <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; 717*4882a593Smuzhiyun }; 718*4882a593Smuzhiyun }; 719*4882a593Smuzhiyun 720*4882a593Smuzhiyun usart3 { 721*4882a593Smuzhiyun pinctrl_usart3: usart3-0 { 722*4882a593Smuzhiyun atmel,pins = 723*4882a593Smuzhiyun <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>, 724*4882a593Smuzhiyun <AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; 725*4882a593Smuzhiyun }; 726*4882a593Smuzhiyun 727*4882a593Smuzhiyun pinctrl_usart3_rts: usart3_rts-0 { 728*4882a593Smuzhiyun atmel,pins = 729*4882a593Smuzhiyun <AT91_PIOD 4 AT91_PERIPH_B AT91_PINCTRL_NONE>; 730*4882a593Smuzhiyun }; 731*4882a593Smuzhiyun 732*4882a593Smuzhiyun pinctrl_usart3_cts: usart3_cts-0 { 733*4882a593Smuzhiyun atmel,pins = 734*4882a593Smuzhiyun <AT91_PIOD 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; 735*4882a593Smuzhiyun }; 736*4882a593Smuzhiyun 737*4882a593Smuzhiyun pinctrl_usart3_sck: usart3_sck-0 { 738*4882a593Smuzhiyun atmel,pins = 739*4882a593Smuzhiyun <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>; 740*4882a593Smuzhiyun }; 741*4882a593Smuzhiyun }; 742*4882a593Smuzhiyun 743*4882a593Smuzhiyun pioA: gpio@fffff400 { 744*4882a593Smuzhiyun compatible = "atmel,at91rm9200-gpio"; 745*4882a593Smuzhiyun reg = <0xfffff400 0x200>; 746*4882a593Smuzhiyun interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; 747*4882a593Smuzhiyun #gpio-cells = <2>; 748*4882a593Smuzhiyun gpio-controller; 749*4882a593Smuzhiyun interrupt-controller; 750*4882a593Smuzhiyun #interrupt-cells = <2>; 751*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; 752*4882a593Smuzhiyun }; 753*4882a593Smuzhiyun 754*4882a593Smuzhiyun pioB: gpio@fffff600 { 755*4882a593Smuzhiyun compatible = "atmel,at91rm9200-gpio"; 756*4882a593Smuzhiyun reg = <0xfffff600 0x200>; 757*4882a593Smuzhiyun interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; 758*4882a593Smuzhiyun #gpio-cells = <2>; 759*4882a593Smuzhiyun gpio-controller; 760*4882a593Smuzhiyun interrupt-controller; 761*4882a593Smuzhiyun #interrupt-cells = <2>; 762*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; 763*4882a593Smuzhiyun }; 764*4882a593Smuzhiyun 765*4882a593Smuzhiyun pioC: gpio@fffff800 { 766*4882a593Smuzhiyun compatible = "atmel,at91rm9200-gpio"; 767*4882a593Smuzhiyun reg = <0xfffff800 0x200>; 768*4882a593Smuzhiyun interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; 769*4882a593Smuzhiyun #gpio-cells = <2>; 770*4882a593Smuzhiyun gpio-controller; 771*4882a593Smuzhiyun interrupt-controller; 772*4882a593Smuzhiyun #interrupt-cells = <2>; 773*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; 774*4882a593Smuzhiyun }; 775*4882a593Smuzhiyun 776*4882a593Smuzhiyun pioD: gpio@fffffa00 { 777*4882a593Smuzhiyun compatible = "atmel,at91rm9200-gpio"; 778*4882a593Smuzhiyun reg = <0xfffffa00 0x200>; 779*4882a593Smuzhiyun interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; 780*4882a593Smuzhiyun #gpio-cells = <2>; 781*4882a593Smuzhiyun gpio-controller; 782*4882a593Smuzhiyun interrupt-controller; 783*4882a593Smuzhiyun #interrupt-cells = <2>; 784*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 785*4882a593Smuzhiyun }; 786*4882a593Smuzhiyun }; 787*4882a593Smuzhiyun 788*4882a593Smuzhiyun pmc: pmc@fffffc00 { 789*4882a593Smuzhiyun compatible = "atmel,at91sam9rl-pmc", "syscon"; 790*4882a593Smuzhiyun reg = <0xfffffc00 0x100>; 791*4882a593Smuzhiyun interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 792*4882a593Smuzhiyun #clock-cells = <2>; 793*4882a593Smuzhiyun clocks = <&clk32k>, <&main_xtal>; 794*4882a593Smuzhiyun clock-names = "slow_clk", "main_xtal"; 795*4882a593Smuzhiyun }; 796*4882a593Smuzhiyun 797*4882a593Smuzhiyun rstc@fffffd00 { 798*4882a593Smuzhiyun compatible = "atmel,at91sam9260-rstc"; 799*4882a593Smuzhiyun reg = <0xfffffd00 0x10>; 800*4882a593Smuzhiyun clocks = <&clk32k>; 801*4882a593Smuzhiyun }; 802*4882a593Smuzhiyun 803*4882a593Smuzhiyun shdwc@fffffd10 { 804*4882a593Smuzhiyun compatible = "atmel,at91sam9260-shdwc"; 805*4882a593Smuzhiyun reg = <0xfffffd10 0x10>; 806*4882a593Smuzhiyun clocks = <&clk32k>; 807*4882a593Smuzhiyun }; 808*4882a593Smuzhiyun 809*4882a593Smuzhiyun pit: timer@fffffd30 { 810*4882a593Smuzhiyun compatible = "atmel,at91sam9260-pit"; 811*4882a593Smuzhiyun reg = <0xfffffd30 0xf>; 812*4882a593Smuzhiyun interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 813*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 814*4882a593Smuzhiyun }; 815*4882a593Smuzhiyun 816*4882a593Smuzhiyun watchdog@fffffd40 { 817*4882a593Smuzhiyun compatible = "atmel,at91sam9260-wdt"; 818*4882a593Smuzhiyun reg = <0xfffffd40 0x10>; 819*4882a593Smuzhiyun interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 820*4882a593Smuzhiyun clocks = <&clk32k>; 821*4882a593Smuzhiyun status = "disabled"; 822*4882a593Smuzhiyun }; 823*4882a593Smuzhiyun 824*4882a593Smuzhiyun clk32k: sckc@fffffd50 { 825*4882a593Smuzhiyun compatible = "atmel,at91sam9x5-sckc"; 826*4882a593Smuzhiyun reg = <0xfffffd50 0x4>; 827*4882a593Smuzhiyun clocks = <&slow_xtal>; 828*4882a593Smuzhiyun #clock-cells = <0>; 829*4882a593Smuzhiyun }; 830*4882a593Smuzhiyun 831*4882a593Smuzhiyun rtc@fffffd20 { 832*4882a593Smuzhiyun compatible = "atmel,at91sam9260-rtt"; 833*4882a593Smuzhiyun reg = <0xfffffd20 0x10>; 834*4882a593Smuzhiyun interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 835*4882a593Smuzhiyun clocks = <&clk32k>; 836*4882a593Smuzhiyun status = "disabled"; 837*4882a593Smuzhiyun }; 838*4882a593Smuzhiyun 839*4882a593Smuzhiyun gpbr: syscon@fffffd60 { 840*4882a593Smuzhiyun compatible = "atmel,at91sam9260-gpbr", "syscon"; 841*4882a593Smuzhiyun reg = <0xfffffd60 0x10>; 842*4882a593Smuzhiyun status = "disabled"; 843*4882a593Smuzhiyun }; 844*4882a593Smuzhiyun 845*4882a593Smuzhiyun rtc@fffffe00 { 846*4882a593Smuzhiyun compatible = "atmel,at91rm9200-rtc"; 847*4882a593Smuzhiyun reg = <0xfffffe00 0x40>; 848*4882a593Smuzhiyun interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 849*4882a593Smuzhiyun clocks = <&clk32k>; 850*4882a593Smuzhiyun status = "disabled"; 851*4882a593Smuzhiyun }; 852*4882a593Smuzhiyun 853*4882a593Smuzhiyun }; 854*4882a593Smuzhiyun }; 855*4882a593Smuzhiyun 856*4882a593Smuzhiyun i2c-gpio-0 { 857*4882a593Smuzhiyun compatible = "i2c-gpio"; 858*4882a593Smuzhiyun gpios = <&pioA 23 GPIO_ACTIVE_HIGH>, /* sda */ 859*4882a593Smuzhiyun <&pioA 24 GPIO_ACTIVE_HIGH>; /* scl */ 860*4882a593Smuzhiyun i2c-gpio,sda-open-drain; 861*4882a593Smuzhiyun i2c-gpio,scl-open-drain; 862*4882a593Smuzhiyun i2c-gpio,delay-us = <2>; /* ~100 kHz */ 863*4882a593Smuzhiyun #address-cells = <1>; 864*4882a593Smuzhiyun #size-cells = <0>; 865*4882a593Smuzhiyun pinctrl-names = "default"; 866*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c_gpio0>; 867*4882a593Smuzhiyun status = "disabled"; 868*4882a593Smuzhiyun }; 869*4882a593Smuzhiyun 870*4882a593Smuzhiyun i2c-gpio-1 { 871*4882a593Smuzhiyun compatible = "i2c-gpio"; 872*4882a593Smuzhiyun gpios = <&pioD 10 GPIO_ACTIVE_HIGH>, /* sda */ 873*4882a593Smuzhiyun <&pioD 11 GPIO_ACTIVE_HIGH>; /* scl */ 874*4882a593Smuzhiyun i2c-gpio,sda-open-drain; 875*4882a593Smuzhiyun i2c-gpio,scl-open-drain; 876*4882a593Smuzhiyun i2c-gpio,delay-us = <2>; /* ~100 kHz */ 877*4882a593Smuzhiyun #address-cells = <1>; 878*4882a593Smuzhiyun #size-cells = <0>; 879*4882a593Smuzhiyun pinctrl-names = "default"; 880*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c_gpio1>; 881*4882a593Smuzhiyun status = "disabled"; 882*4882a593Smuzhiyun }; 883*4882a593Smuzhiyun}; 884