1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include "at91sam9260.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun model = "Atmel AT91SAM9G20 family SoC"; 12*4882a593Smuzhiyun compatible = "atmel,at91sam9g20"; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun memory@20000000 { 15*4882a593Smuzhiyun reg = <0x20000000 0x08000000>; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun sram0: sram@2ff000 { 19*4882a593Smuzhiyun status = "disabled"; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun sram1: sram@2fc000 { 23*4882a593Smuzhiyun compatible = "mmio-sram"; 24*4882a593Smuzhiyun reg = <0x002fc000 0x8000>; 25*4882a593Smuzhiyun #address-cells = <1>; 26*4882a593Smuzhiyun #size-cells = <1>; 27*4882a593Smuzhiyun ranges = <0 0x002fc000 0x8000>; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun ahb { 31*4882a593Smuzhiyun apb { 32*4882a593Smuzhiyun i2c0: i2c@fffac000 { 33*4882a593Smuzhiyun compatible = "atmel,at91sam9g20-i2c"; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun ssc0: ssc@fffbc000 { 37*4882a593Smuzhiyun compatible = "atmel,at91sam9rl-ssc"; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun adc0: adc@fffe0000 { 41*4882a593Smuzhiyun atmel,adc-startup-time = <40>; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun pmc: pmc@fffffc00 { 45*4882a593Smuzhiyun compatible = "atmel,at91sam9g20-pmc", "atmel,at91sam9260-pmc", "syscon"; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun}; 50