xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/at91sam9261.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * at91sam9261.dtsi - Device Tree Include file for AT91SAM9261 SoC
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun *  Copyright (C) 2013 Jean-Jacques Hiblot <jjhiblot@traphandler.com>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun#include <dt-bindings/pinctrl/at91.h>
9*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h>
10*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
11*4882a593Smuzhiyun#include <dt-bindings/clock/at91.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun/ {
14*4882a593Smuzhiyun	#address-cells = <1>;
15*4882a593Smuzhiyun	#size-cells = <1>;
16*4882a593Smuzhiyun	model = "Atmel AT91SAM9261 family SoC";
17*4882a593Smuzhiyun	compatible = "atmel,at91sam9261";
18*4882a593Smuzhiyun	interrupt-parent = <&aic>;
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun	aliases {
21*4882a593Smuzhiyun		serial0 = &dbgu;
22*4882a593Smuzhiyun		serial1 = &usart0;
23*4882a593Smuzhiyun		serial2 = &usart1;
24*4882a593Smuzhiyun		serial3 = &usart2;
25*4882a593Smuzhiyun		gpio0 = &pioA;
26*4882a593Smuzhiyun		gpio1 = &pioB;
27*4882a593Smuzhiyun		gpio2 = &pioC;
28*4882a593Smuzhiyun		tcb0 = &tcb0;
29*4882a593Smuzhiyun		i2c0 = &i2c0;
30*4882a593Smuzhiyun		ssc0 = &ssc0;
31*4882a593Smuzhiyun		ssc1 = &ssc1;
32*4882a593Smuzhiyun		ssc2 = &ssc2;
33*4882a593Smuzhiyun	};
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun	cpus {
36*4882a593Smuzhiyun		#address-cells = <1>;
37*4882a593Smuzhiyun		#size-cells = <0>;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun		cpu@0 {
40*4882a593Smuzhiyun			compatible = "arm,arm926ej-s";
41*4882a593Smuzhiyun			device_type = "cpu";
42*4882a593Smuzhiyun			reg = <0>;
43*4882a593Smuzhiyun		};
44*4882a593Smuzhiyun	};
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun	memory@20000000 {
47*4882a593Smuzhiyun		device_type = "memory";
48*4882a593Smuzhiyun		reg = <0x20000000 0x08000000>;
49*4882a593Smuzhiyun	};
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun	clocks {
52*4882a593Smuzhiyun		main_xtal: main_xtal {
53*4882a593Smuzhiyun			compatible = "fixed-clock";
54*4882a593Smuzhiyun			#clock-cells = <0>;
55*4882a593Smuzhiyun			clock-frequency = <0>;
56*4882a593Smuzhiyun		};
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun		slow_xtal: slow_xtal {
59*4882a593Smuzhiyun			compatible = "fixed-clock";
60*4882a593Smuzhiyun			#clock-cells = <0>;
61*4882a593Smuzhiyun			clock-frequency = <0>;
62*4882a593Smuzhiyun		};
63*4882a593Smuzhiyun	};
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun	sram: sram@300000 {
66*4882a593Smuzhiyun		compatible = "mmio-sram";
67*4882a593Smuzhiyun		reg = <0x00300000 0x28000>;
68*4882a593Smuzhiyun		#address-cells = <1>;
69*4882a593Smuzhiyun		#size-cells = <1>;
70*4882a593Smuzhiyun		ranges = <0 0x00300000 0x28000>;
71*4882a593Smuzhiyun	};
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun	ahb {
74*4882a593Smuzhiyun		compatible = "simple-bus";
75*4882a593Smuzhiyun		#address-cells = <1>;
76*4882a593Smuzhiyun		#size-cells = <1>;
77*4882a593Smuzhiyun		ranges;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun		usb0: ohci@500000 {
80*4882a593Smuzhiyun			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
81*4882a593Smuzhiyun			reg = <0x00500000 0x100000>;
82*4882a593Smuzhiyun			interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>;
83*4882a593Smuzhiyun			clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_SYSTEM 16>, <&pmc PMC_TYPE_SYSTEM 6>;
84*4882a593Smuzhiyun			clock-names = "ohci_clk", "hclk", "uhpck";
85*4882a593Smuzhiyun			status = "disabled";
86*4882a593Smuzhiyun		};
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun		fb0: fb@600000 {
89*4882a593Smuzhiyun			compatible = "atmel,at91sam9261-lcdc";
90*4882a593Smuzhiyun			reg = <0x00600000 0x1000>;
91*4882a593Smuzhiyun			interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
92*4882a593Smuzhiyun			pinctrl-names = "default";
93*4882a593Smuzhiyun			pinctrl-0 = <&pinctrl_fb>;
94*4882a593Smuzhiyun			clocks = <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_SYSTEM 17>;
95*4882a593Smuzhiyun			clock-names = "lcdc_clk", "hclk";
96*4882a593Smuzhiyun			status = "disabled";
97*4882a593Smuzhiyun		};
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun		ebi: ebi@10000000 {
100*4882a593Smuzhiyun			compatible = "atmel,at91sam9261-ebi";
101*4882a593Smuzhiyun			#address-cells = <2>;
102*4882a593Smuzhiyun			#size-cells = <1>;
103*4882a593Smuzhiyun			atmel,smc = <&smc>;
104*4882a593Smuzhiyun			atmel,matrix = <&matrix>;
105*4882a593Smuzhiyun			reg = <0x10000000 0x80000000>;
106*4882a593Smuzhiyun			ranges = <0x0 0x0 0x10000000 0x10000000
107*4882a593Smuzhiyun				  0x1 0x0 0x20000000 0x10000000
108*4882a593Smuzhiyun				  0x2 0x0 0x30000000 0x10000000
109*4882a593Smuzhiyun				  0x3 0x0 0x40000000 0x10000000
110*4882a593Smuzhiyun				  0x4 0x0 0x50000000 0x10000000
111*4882a593Smuzhiyun				  0x5 0x0 0x60000000 0x10000000
112*4882a593Smuzhiyun				  0x6 0x0 0x70000000 0x10000000
113*4882a593Smuzhiyun				  0x7 0x0 0x80000000 0x10000000>;
114*4882a593Smuzhiyun			clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
115*4882a593Smuzhiyun			status = "disabled";
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun			nand_controller: nand-controller {
118*4882a593Smuzhiyun				compatible = "atmel,at91sam9261-nand-controller";
119*4882a593Smuzhiyun				#address-cells = <2>;
120*4882a593Smuzhiyun				#size-cells = <1>;
121*4882a593Smuzhiyun				ranges;
122*4882a593Smuzhiyun				status = "disabled";
123*4882a593Smuzhiyun			};
124*4882a593Smuzhiyun		};
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun		apb {
127*4882a593Smuzhiyun			compatible = "simple-bus";
128*4882a593Smuzhiyun			#address-cells = <1>;
129*4882a593Smuzhiyun			#size-cells = <1>;
130*4882a593Smuzhiyun			ranges;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun			tcb0: timer@fffa0000 {
133*4882a593Smuzhiyun				compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
134*4882a593Smuzhiyun				#address-cells = <1>;
135*4882a593Smuzhiyun				#size-cells = <0>;
136*4882a593Smuzhiyun				reg = <0xfffa0000 0x100>;
137*4882a593Smuzhiyun				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>,
138*4882a593Smuzhiyun					     <18 IRQ_TYPE_LEVEL_HIGH 0>,
139*4882a593Smuzhiyun					     <19 IRQ_TYPE_LEVEL_HIGH 0>;
140*4882a593Smuzhiyun				clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 19>, <&slow_xtal>;
141*4882a593Smuzhiyun				clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
142*4882a593Smuzhiyun			};
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun			usb1: gadget@fffa4000 {
145*4882a593Smuzhiyun				compatible = "atmel,at91sam9261-udc";
146*4882a593Smuzhiyun				reg = <0xfffa4000 0x4000>;
147*4882a593Smuzhiyun				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
148*4882a593Smuzhiyun				clocks = <&pmc PMC_TYPE_PERIPHERAL 10>, <&pmc PMC_TYPE_SYSTEM 7>;
149*4882a593Smuzhiyun				clock-names = "pclk", "hclk";
150*4882a593Smuzhiyun				atmel,matrix = <&matrix>;
151*4882a593Smuzhiyun				status = "disabled";
152*4882a593Smuzhiyun			};
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun			mmc0: mmc@fffa8000 {
155*4882a593Smuzhiyun				compatible = "atmel,hsmci";
156*4882a593Smuzhiyun				reg = <0xfffa8000 0x600>;
157*4882a593Smuzhiyun				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
158*4882a593Smuzhiyun				pinctrl-names = "default";
159*4882a593Smuzhiyun				pinctrl-0 = <&pinctrl_mmc0_clk>, <&pinctrl_mmc0_slot0_cmd_dat0>, <&pinctrl_mmc0_slot0_dat1_3>;
160*4882a593Smuzhiyun				#address-cells = <1>;
161*4882a593Smuzhiyun				#size-cells = <0>;
162*4882a593Smuzhiyun				clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
163*4882a593Smuzhiyun				clock-names = "mci_clk";
164*4882a593Smuzhiyun				status = "disabled";
165*4882a593Smuzhiyun			};
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun			i2c0: i2c@fffac000 {
168*4882a593Smuzhiyun				compatible = "atmel,at91sam9261-i2c";
169*4882a593Smuzhiyun				pinctrl-names = "default";
170*4882a593Smuzhiyun				pinctrl-0 = <&pinctrl_i2c_twi>;
171*4882a593Smuzhiyun				reg = <0xfffac000 0x100>;
172*4882a593Smuzhiyun				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
173*4882a593Smuzhiyun				#address-cells = <1>;
174*4882a593Smuzhiyun				#size-cells = <0>;
175*4882a593Smuzhiyun				clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
176*4882a593Smuzhiyun				status = "disabled";
177*4882a593Smuzhiyun			};
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun			usart0: serial@fffb0000 {
180*4882a593Smuzhiyun				compatible = "atmel,at91sam9260-usart";
181*4882a593Smuzhiyun				reg = <0xfffb0000 0x200>;
182*4882a593Smuzhiyun				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
183*4882a593Smuzhiyun				atmel,use-dma-rx;
184*4882a593Smuzhiyun				atmel,use-dma-tx;
185*4882a593Smuzhiyun				pinctrl-names = "default";
186*4882a593Smuzhiyun				pinctrl-0 = <&pinctrl_usart0>;
187*4882a593Smuzhiyun				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
188*4882a593Smuzhiyun				clock-names = "usart";
189*4882a593Smuzhiyun				status = "disabled";
190*4882a593Smuzhiyun			};
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun			usart1: serial@fffb4000 {
193*4882a593Smuzhiyun				compatible = "atmel,at91sam9260-usart";
194*4882a593Smuzhiyun				reg = <0xfffb4000 0x200>;
195*4882a593Smuzhiyun				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
196*4882a593Smuzhiyun				atmel,use-dma-rx;
197*4882a593Smuzhiyun				atmel,use-dma-tx;
198*4882a593Smuzhiyun				pinctrl-names = "default";
199*4882a593Smuzhiyun				pinctrl-0 = <&pinctrl_usart1>;
200*4882a593Smuzhiyun				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
201*4882a593Smuzhiyun				clock-names = "usart";
202*4882a593Smuzhiyun				status = "disabled";
203*4882a593Smuzhiyun			};
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun			usart2: serial@fffb8000{
206*4882a593Smuzhiyun				compatible = "atmel,at91sam9260-usart";
207*4882a593Smuzhiyun				reg = <0xfffb8000 0x200>;
208*4882a593Smuzhiyun				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
209*4882a593Smuzhiyun				atmel,use-dma-rx;
210*4882a593Smuzhiyun				atmel,use-dma-tx;
211*4882a593Smuzhiyun				pinctrl-names = "default";
212*4882a593Smuzhiyun				pinctrl-0 = <&pinctrl_usart2>;
213*4882a593Smuzhiyun				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
214*4882a593Smuzhiyun				clock-names = "usart";
215*4882a593Smuzhiyun				status = "disabled";
216*4882a593Smuzhiyun			};
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun			ssc0: ssc@fffbc000 {
219*4882a593Smuzhiyun				compatible = "atmel,at91rm9200-ssc";
220*4882a593Smuzhiyun				reg = <0xfffbc000 0x4000>;
221*4882a593Smuzhiyun				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
222*4882a593Smuzhiyun				pinctrl-names = "default";
223*4882a593Smuzhiyun				pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
224*4882a593Smuzhiyun				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
225*4882a593Smuzhiyun				clock-names = "pclk";
226*4882a593Smuzhiyun				status = "disabled";
227*4882a593Smuzhiyun			};
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun			ssc1: ssc@fffc0000 {
230*4882a593Smuzhiyun				compatible = "atmel,at91rm9200-ssc";
231*4882a593Smuzhiyun				reg = <0xfffc0000 0x4000>;
232*4882a593Smuzhiyun				interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
233*4882a593Smuzhiyun				pinctrl-names = "default";
234*4882a593Smuzhiyun				pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
235*4882a593Smuzhiyun				clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
236*4882a593Smuzhiyun				clock-names = "pclk";
237*4882a593Smuzhiyun				status = "disabled";
238*4882a593Smuzhiyun			};
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun			ssc2: ssc@fffc4000 {
241*4882a593Smuzhiyun				compatible = "atmel,at91rm9200-ssc";
242*4882a593Smuzhiyun				reg = <0xfffc4000 0x4000>;
243*4882a593Smuzhiyun				interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
244*4882a593Smuzhiyun				pinctrl-names = "default";
245*4882a593Smuzhiyun				pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
246*4882a593Smuzhiyun				clocks = <&pmc PMC_TYPE_PERIPHERAL 16>;
247*4882a593Smuzhiyun				clock-names = "pclk";
248*4882a593Smuzhiyun				status = "disabled";
249*4882a593Smuzhiyun			};
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun			spi0: spi@fffc8000 {
252*4882a593Smuzhiyun				#address-cells = <1>;
253*4882a593Smuzhiyun				#size-cells = <0>;
254*4882a593Smuzhiyun				compatible = "atmel,at91rm9200-spi";
255*4882a593Smuzhiyun				reg = <0xfffc8000 0x200>;
256*4882a593Smuzhiyun				cs-gpios = <0>, <0>, <0>, <0>;
257*4882a593Smuzhiyun				interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
258*4882a593Smuzhiyun				pinctrl-names = "default";
259*4882a593Smuzhiyun				pinctrl-0 = <&pinctrl_spi0>;
260*4882a593Smuzhiyun				clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
261*4882a593Smuzhiyun				clock-names = "spi_clk";
262*4882a593Smuzhiyun				status = "disabled";
263*4882a593Smuzhiyun			};
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun			spi1: spi@fffcc000 {
266*4882a593Smuzhiyun				#address-cells = <1>;
267*4882a593Smuzhiyun				#size-cells = <0>;
268*4882a593Smuzhiyun				compatible = "atmel,at91rm9200-spi";
269*4882a593Smuzhiyun				reg = <0xfffcc000 0x200>;
270*4882a593Smuzhiyun				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
271*4882a593Smuzhiyun				pinctrl-names = "default";
272*4882a593Smuzhiyun				pinctrl-0 = <&pinctrl_spi1>;
273*4882a593Smuzhiyun				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
274*4882a593Smuzhiyun				clock-names = "spi_clk";
275*4882a593Smuzhiyun				status = "disabled";
276*4882a593Smuzhiyun			};
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun			ramc: ramc@ffffea00 {
279*4882a593Smuzhiyun				compatible = "atmel,at91sam9260-sdramc";
280*4882a593Smuzhiyun				reg = <0xffffea00 0x200>;
281*4882a593Smuzhiyun			};
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun			smc: smc@ffffec00 {
284*4882a593Smuzhiyun				compatible = "atmel,at91sam9260-smc", "syscon";
285*4882a593Smuzhiyun				reg = <0xffffec00 0x200>;
286*4882a593Smuzhiyun			};
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun			matrix: matrix@ffffee00 {
289*4882a593Smuzhiyun				compatible = "atmel,at91sam9261-matrix", "syscon";
290*4882a593Smuzhiyun				reg = <0xffffee00 0x200>;
291*4882a593Smuzhiyun			};
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun			aic: interrupt-controller@fffff000 {
294*4882a593Smuzhiyun				#interrupt-cells = <3>;
295*4882a593Smuzhiyun				compatible = "atmel,at91rm9200-aic";
296*4882a593Smuzhiyun				interrupt-controller;
297*4882a593Smuzhiyun				reg = <0xfffff000 0x200>;
298*4882a593Smuzhiyun				atmel,external-irqs = <29 30 31>;
299*4882a593Smuzhiyun			};
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun			dbgu: serial@fffff200 {
302*4882a593Smuzhiyun				compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
303*4882a593Smuzhiyun				reg = <0xfffff200 0x200>;
304*4882a593Smuzhiyun				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
305*4882a593Smuzhiyun				pinctrl-names = "default";
306*4882a593Smuzhiyun				pinctrl-0 = <&pinctrl_dbgu>;
307*4882a593Smuzhiyun				clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
308*4882a593Smuzhiyun				clock-names = "usart";
309*4882a593Smuzhiyun				status = "disabled";
310*4882a593Smuzhiyun			};
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun			pinctrl@fffff400 {
313*4882a593Smuzhiyun				#address-cells = <1>;
314*4882a593Smuzhiyun				#size-cells = <1>;
315*4882a593Smuzhiyun				compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
316*4882a593Smuzhiyun				ranges = <0xfffff400 0xfffff400 0x600>;
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun				atmel,mux-mask =
319*4882a593Smuzhiyun				      /*    A         B     */
320*4882a593Smuzhiyun				      <0xffffffff 0xfffffff7>,  /* pioA */
321*4882a593Smuzhiyun				      <0xffffffff 0xfffffff4>,  /* pioB */
322*4882a593Smuzhiyun				      <0xffffffff 0xffffff07>;  /* pioC */
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun				/* shared pinctrl settings */
325*4882a593Smuzhiyun				dbgu {
326*4882a593Smuzhiyun					pinctrl_dbgu: dbgu-0 {
327*4882a593Smuzhiyun						atmel,pins =
328*4882a593Smuzhiyun							<AT91_PIOA 9  AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
329*4882a593Smuzhiyun							<AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
330*4882a593Smuzhiyun					};
331*4882a593Smuzhiyun				};
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun				usart0 {
334*4882a593Smuzhiyun					pinctrl_usart0: usart0-0 {
335*4882a593Smuzhiyun						atmel,pins =
336*4882a593Smuzhiyun							<AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
337*4882a593Smuzhiyun							<AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
338*4882a593Smuzhiyun					};
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun					pinctrl_usart0_rts: usart0_rts-0 {
341*4882a593Smuzhiyun						atmel,pins =
342*4882a593Smuzhiyun							<AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
343*4882a593Smuzhiyun					};
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun					pinctrl_usart0_cts: usart0_cts-0 {
346*4882a593Smuzhiyun						atmel,pins =
347*4882a593Smuzhiyun							<AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE>;
348*4882a593Smuzhiyun					};
349*4882a593Smuzhiyun				};
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun				usart1 {
352*4882a593Smuzhiyun					pinctrl_usart1: usart1-0 {
353*4882a593Smuzhiyun						atmel,pins =
354*4882a593Smuzhiyun							<AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
355*4882a593Smuzhiyun							<AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
356*4882a593Smuzhiyun					};
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun					pinctrl_usart1_rts: usart1_rts-0 {
359*4882a593Smuzhiyun						atmel,pins =
360*4882a593Smuzhiyun							<AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_NONE>;
361*4882a593Smuzhiyun					};
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun					pinctrl_usart1_cts: usart1_cts-0 {
364*4882a593Smuzhiyun						atmel,pins =
365*4882a593Smuzhiyun							<AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
366*4882a593Smuzhiyun					};
367*4882a593Smuzhiyun				};
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun				usart2 {
370*4882a593Smuzhiyun					pinctrl_usart2: usart2-0 {
371*4882a593Smuzhiyun						atmel,pins =
372*4882a593Smuzhiyun							<AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
373*4882a593Smuzhiyun							<AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
374*4882a593Smuzhiyun					};
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun					pinctrl_usart2_rts: usart2_rts-0 {
377*4882a593Smuzhiyun						atmel,pins =
378*4882a593Smuzhiyun							<AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE>;
379*4882a593Smuzhiyun					};
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun					pinctrl_usart2_cts: usart2_cts-0 {
382*4882a593Smuzhiyun						atmel,pins =
383*4882a593Smuzhiyun							<AT91_PIOA 16 AT91_PERIPH_B AT91_PINCTRL_NONE>;
384*4882a593Smuzhiyun					};
385*4882a593Smuzhiyun				};
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun				nand {
388*4882a593Smuzhiyun					pinctrl_nand_rb: nand-rb-0 {
389*4882a593Smuzhiyun						atmel,pins =
390*4882a593Smuzhiyun							<AT91_PIOC 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
391*4882a593Smuzhiyun					};
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun					pinctrl_nand_cs: nand-cs-0 {
394*4882a593Smuzhiyun						atmel,pins =
395*4882a593Smuzhiyun							<AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
396*4882a593Smuzhiyun					};
397*4882a593Smuzhiyun				};
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun				mmc0 {
400*4882a593Smuzhiyun					pinctrl_mmc0_clk: mmc0_clk-0 {
401*4882a593Smuzhiyun						atmel,pins =
402*4882a593Smuzhiyun							<AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
403*4882a593Smuzhiyun					};
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun					pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
406*4882a593Smuzhiyun						atmel,pins =
407*4882a593Smuzhiyun							<AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>,
408*4882a593Smuzhiyun							<AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
409*4882a593Smuzhiyun					};
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun					pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
412*4882a593Smuzhiyun						atmel,pins =
413*4882a593Smuzhiyun							<AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>,
414*4882a593Smuzhiyun							<AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>,
415*4882a593Smuzhiyun							<AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
416*4882a593Smuzhiyun					};
417*4882a593Smuzhiyun					};
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun				ssc0 {
420*4882a593Smuzhiyun					pinctrl_ssc0_tx: ssc0_tx-0 {
421*4882a593Smuzhiyun						atmel,pins =
422*4882a593Smuzhiyun							<AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>,
423*4882a593Smuzhiyun							<AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE>,
424*4882a593Smuzhiyun							<AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
425*4882a593Smuzhiyun					};
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun					pinctrl_ssc0_rx: ssc0_rx-0 {
428*4882a593Smuzhiyun						atmel,pins =
429*4882a593Smuzhiyun							<AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>,
430*4882a593Smuzhiyun							<AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>,
431*4882a593Smuzhiyun							<AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
432*4882a593Smuzhiyun					};
433*4882a593Smuzhiyun				};
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun				ssc1 {
436*4882a593Smuzhiyun					pinctrl_ssc1_tx: ssc1_tx-0 {
437*4882a593Smuzhiyun						atmel,pins =
438*4882a593Smuzhiyun							<AT91_PIOA 17 AT91_PERIPH_B AT91_PINCTRL_NONE>,
439*4882a593Smuzhiyun							<AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE>,
440*4882a593Smuzhiyun							<AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
441*4882a593Smuzhiyun					};
442*4882a593Smuzhiyun
443*4882a593Smuzhiyun					pinctrl_ssc1_rx: ssc1_rx-0 {
444*4882a593Smuzhiyun						atmel,pins =
445*4882a593Smuzhiyun							<AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>,
446*4882a593Smuzhiyun							<AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>,
447*4882a593Smuzhiyun							<AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
448*4882a593Smuzhiyun					};
449*4882a593Smuzhiyun				};
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun				ssc2 {
452*4882a593Smuzhiyun					pinctrl_ssc2_tx: ssc2_tx-0 {
453*4882a593Smuzhiyun						atmel,pins =
454*4882a593Smuzhiyun							<AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>,
455*4882a593Smuzhiyun							<AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>,
456*4882a593Smuzhiyun							<AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>;
457*4882a593Smuzhiyun					};
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun					pinctrl_ssc2_rx: ssc2_rx-0 {
460*4882a593Smuzhiyun						atmel,pins =
461*4882a593Smuzhiyun							<AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE>,
462*4882a593Smuzhiyun							<AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE>,
463*4882a593Smuzhiyun							<AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE>;
464*4882a593Smuzhiyun					};
465*4882a593Smuzhiyun				};
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun				spi0 {
468*4882a593Smuzhiyun					pinctrl_spi0: spi0-0 {
469*4882a593Smuzhiyun						atmel,pins =
470*4882a593Smuzhiyun							<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>,
471*4882a593Smuzhiyun							<AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>,
472*4882a593Smuzhiyun							<AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;
473*4882a593Smuzhiyun					};
474*4882a593Smuzhiyun					};
475*4882a593Smuzhiyun
476*4882a593Smuzhiyun				spi1 {
477*4882a593Smuzhiyun					pinctrl_spi1: spi1-0 {
478*4882a593Smuzhiyun						atmel,pins =
479*4882a593Smuzhiyun							<AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>,
480*4882a593Smuzhiyun							<AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_NONE>,
481*4882a593Smuzhiyun							<AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
482*4882a593Smuzhiyun					};
483*4882a593Smuzhiyun				};
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun				tcb0 {
486*4882a593Smuzhiyun					pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
487*4882a593Smuzhiyun						atmel,pins = <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE>;
488*4882a593Smuzhiyun					};
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun					pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
491*4882a593Smuzhiyun						atmel,pins = <AT91_PIOC 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
492*4882a593Smuzhiyun					};
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun					pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
495*4882a593Smuzhiyun						atmel,pins = <AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
496*4882a593Smuzhiyun					};
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun					pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
499*4882a593Smuzhiyun						atmel,pins = <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
500*4882a593Smuzhiyun					};
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun					pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
503*4882a593Smuzhiyun						atmel,pins = <AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>;
504*4882a593Smuzhiyun					};
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun					pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
507*4882a593Smuzhiyun						atmel,pins = <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>;
508*4882a593Smuzhiyun					};
509*4882a593Smuzhiyun
510*4882a593Smuzhiyun					pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
511*4882a593Smuzhiyun						atmel,pins = <AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE>;
512*4882a593Smuzhiyun					};
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun					pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
515*4882a593Smuzhiyun						atmel,pins = <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
516*4882a593Smuzhiyun					};
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun					pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
519*4882a593Smuzhiyun						atmel,pins = <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>;
520*4882a593Smuzhiyun					};
521*4882a593Smuzhiyun				};
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun				i2c0 {
524*4882a593Smuzhiyun					pinctrl_i2c_bitbang: i2c-0-bitbang {
525*4882a593Smuzhiyun						atmel,pins =
526*4882a593Smuzhiyun							<AT91_PIOA 7 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>,
527*4882a593Smuzhiyun							<AT91_PIOA 8 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
528*4882a593Smuzhiyun					};
529*4882a593Smuzhiyun					pinctrl_i2c_twi: i2c-0-twi {
530*4882a593Smuzhiyun						atmel,pins =
531*4882a593Smuzhiyun							<AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE>,
532*4882a593Smuzhiyun							<AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>;
533*4882a593Smuzhiyun					};
534*4882a593Smuzhiyun				};
535*4882a593Smuzhiyun
536*4882a593Smuzhiyun				fb {
537*4882a593Smuzhiyun					pinctrl_fb: fb-0 {
538*4882a593Smuzhiyun						atmel,pins =
539*4882a593Smuzhiyun							<AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE>,
540*4882a593Smuzhiyun							<AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>,
541*4882a593Smuzhiyun							<AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE>,
542*4882a593Smuzhiyun							<AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>,
543*4882a593Smuzhiyun							<AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>,
544*4882a593Smuzhiyun							<AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>,
545*4882a593Smuzhiyun							<AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>,
546*4882a593Smuzhiyun							<AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>,
547*4882a593Smuzhiyun							<AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE>,
548*4882a593Smuzhiyun							<AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>,
549*4882a593Smuzhiyun							<AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE>,
550*4882a593Smuzhiyun							<AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>,
551*4882a593Smuzhiyun							<AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>,
552*4882a593Smuzhiyun							<AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE>,
553*4882a593Smuzhiyun							<AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE>,
554*4882a593Smuzhiyun							<AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE>,
555*4882a593Smuzhiyun							<AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE>,
556*4882a593Smuzhiyun							<AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE>,
557*4882a593Smuzhiyun							<AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE>,
558*4882a593Smuzhiyun							<AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE>,
559*4882a593Smuzhiyun							<AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
560*4882a593Smuzhiyun					};
561*4882a593Smuzhiyun				};
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun				pioA: gpio@fffff400 {
564*4882a593Smuzhiyun					compatible = "atmel,at91rm9200-gpio";
565*4882a593Smuzhiyun					reg = <0xfffff400 0x200>;
566*4882a593Smuzhiyun					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
567*4882a593Smuzhiyun					#gpio-cells = <2>;
568*4882a593Smuzhiyun					gpio-controller;
569*4882a593Smuzhiyun					interrupt-controller;
570*4882a593Smuzhiyun					#interrupt-cells = <2>;
571*4882a593Smuzhiyun					clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
572*4882a593Smuzhiyun				};
573*4882a593Smuzhiyun
574*4882a593Smuzhiyun				pioB: gpio@fffff600 {
575*4882a593Smuzhiyun					compatible = "atmel,at91rm9200-gpio";
576*4882a593Smuzhiyun					reg = <0xfffff600 0x200>;
577*4882a593Smuzhiyun					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
578*4882a593Smuzhiyun					#gpio-cells = <2>;
579*4882a593Smuzhiyun					gpio-controller;
580*4882a593Smuzhiyun					interrupt-controller;
581*4882a593Smuzhiyun					#interrupt-cells = <2>;
582*4882a593Smuzhiyun					clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
583*4882a593Smuzhiyun				};
584*4882a593Smuzhiyun
585*4882a593Smuzhiyun				pioC: gpio@fffff800 {
586*4882a593Smuzhiyun					compatible = "atmel,at91rm9200-gpio";
587*4882a593Smuzhiyun					reg = <0xfffff800 0x200>;
588*4882a593Smuzhiyun					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
589*4882a593Smuzhiyun					#gpio-cells = <2>;
590*4882a593Smuzhiyun					gpio-controller;
591*4882a593Smuzhiyun					interrupt-controller;
592*4882a593Smuzhiyun					#interrupt-cells = <2>;
593*4882a593Smuzhiyun					clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
594*4882a593Smuzhiyun				};
595*4882a593Smuzhiyun			};
596*4882a593Smuzhiyun
597*4882a593Smuzhiyun			pmc: pmc@fffffc00 {
598*4882a593Smuzhiyun				compatible = "atmel,at91sam9261-pmc", "syscon";
599*4882a593Smuzhiyun				reg = <0xfffffc00 0x100>;
600*4882a593Smuzhiyun				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
601*4882a593Smuzhiyun				#clock-cells = <2>;
602*4882a593Smuzhiyun				clocks = <&slow_xtal>, <&main_xtal>;
603*4882a593Smuzhiyun				clock-names = "slow_xtal", "main_xtal";
604*4882a593Smuzhiyun			};
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun			rstc@fffffd00 {
607*4882a593Smuzhiyun				compatible = "atmel,at91sam9260-rstc";
608*4882a593Smuzhiyun				reg = <0xfffffd00 0x10>;
609*4882a593Smuzhiyun				clocks = <&slow_xtal>;
610*4882a593Smuzhiyun			};
611*4882a593Smuzhiyun
612*4882a593Smuzhiyun			shdwc@fffffd10 {
613*4882a593Smuzhiyun				compatible = "atmel,at91sam9260-shdwc";
614*4882a593Smuzhiyun				reg = <0xfffffd10 0x10>;
615*4882a593Smuzhiyun				clocks = <&slow_xtal>;
616*4882a593Smuzhiyun			};
617*4882a593Smuzhiyun
618*4882a593Smuzhiyun			pit: timer@fffffd30 {
619*4882a593Smuzhiyun				compatible = "atmel,at91sam9260-pit";
620*4882a593Smuzhiyun				reg = <0xfffffd30 0xf>;
621*4882a593Smuzhiyun				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
622*4882a593Smuzhiyun				clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
623*4882a593Smuzhiyun			};
624*4882a593Smuzhiyun
625*4882a593Smuzhiyun			rtc@fffffd20 {
626*4882a593Smuzhiyun				compatible = "atmel,at91sam9260-rtt";
627*4882a593Smuzhiyun				reg = <0xfffffd20 0x10>;
628*4882a593Smuzhiyun				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
629*4882a593Smuzhiyun				clocks = <&slow_xtal>;
630*4882a593Smuzhiyun				status = "disabled";
631*4882a593Smuzhiyun			};
632*4882a593Smuzhiyun
633*4882a593Smuzhiyun			watchdog@fffffd40 {
634*4882a593Smuzhiyun				compatible = "atmel,at91sam9260-wdt";
635*4882a593Smuzhiyun				reg = <0xfffffd40 0x10>;
636*4882a593Smuzhiyun				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
637*4882a593Smuzhiyun				clocks = <&slow_xtal>;
638*4882a593Smuzhiyun				status = "disabled";
639*4882a593Smuzhiyun			};
640*4882a593Smuzhiyun
641*4882a593Smuzhiyun			gpbr: syscon@fffffd50 {
642*4882a593Smuzhiyun				compatible = "atmel,at91sam9260-gpbr", "syscon";
643*4882a593Smuzhiyun				reg = <0xfffffd50 0x10>;
644*4882a593Smuzhiyun				status = "disabled";
645*4882a593Smuzhiyun			};
646*4882a593Smuzhiyun		};
647*4882a593Smuzhiyun	};
648*4882a593Smuzhiyun
649*4882a593Smuzhiyun	i2c-gpio-0 {
650*4882a593Smuzhiyun		compatible = "i2c-gpio";
651*4882a593Smuzhiyun		pinctrl-names = "default";
652*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_i2c_bitbang>;
653*4882a593Smuzhiyun		gpios = <&pioA 7 GPIO_ACTIVE_HIGH>, /* sda */
654*4882a593Smuzhiyun			<&pioA 8 GPIO_ACTIVE_HIGH>; /* scl */
655*4882a593Smuzhiyun		i2c-gpio,sda-open-drain;
656*4882a593Smuzhiyun		i2c-gpio,scl-open-drain;
657*4882a593Smuzhiyun		i2c-gpio,delay-us = <2>;	/* ~100 kHz */
658*4882a593Smuzhiyun		#address-cells = <1>;
659*4882a593Smuzhiyun		#size-cells = <0>;
660*4882a593Smuzhiyun		status = "disabled";
661*4882a593Smuzhiyun	};
662*4882a593Smuzhiyun};
663