1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2011 Atmel, 6*4882a593Smuzhiyun * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>, 7*4882a593Smuzhiyun * 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun#include <dt-bindings/pinctrl/at91.h> 11*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 12*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 13*4882a593Smuzhiyun#include <dt-bindings/clock/at91.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun/ { 16*4882a593Smuzhiyun #address-cells = <1>; 17*4882a593Smuzhiyun #size-cells = <1>; 18*4882a593Smuzhiyun model = "Atmel AT91SAM9260 family SoC"; 19*4882a593Smuzhiyun compatible = "atmel,at91sam9260"; 20*4882a593Smuzhiyun interrupt-parent = <&aic>; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun aliases { 23*4882a593Smuzhiyun serial0 = &dbgu; 24*4882a593Smuzhiyun serial1 = &usart0; 25*4882a593Smuzhiyun serial2 = &usart1; 26*4882a593Smuzhiyun serial3 = &usart2; 27*4882a593Smuzhiyun serial4 = &usart3; 28*4882a593Smuzhiyun serial5 = &uart0; 29*4882a593Smuzhiyun serial6 = &uart1; 30*4882a593Smuzhiyun gpio0 = &pioA; 31*4882a593Smuzhiyun gpio1 = &pioB; 32*4882a593Smuzhiyun gpio2 = &pioC; 33*4882a593Smuzhiyun tcb0 = &tcb0; 34*4882a593Smuzhiyun tcb1 = &tcb1; 35*4882a593Smuzhiyun i2c0 = &i2c0; 36*4882a593Smuzhiyun ssc0 = &ssc0; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun cpus { 39*4882a593Smuzhiyun #address-cells = <1>; 40*4882a593Smuzhiyun #size-cells = <0>; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun cpu@0 { 43*4882a593Smuzhiyun compatible = "arm,arm926ej-s"; 44*4882a593Smuzhiyun device_type = "cpu"; 45*4882a593Smuzhiyun reg = <0>; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun memory@20000000 { 50*4882a593Smuzhiyun device_type = "memory"; 51*4882a593Smuzhiyun reg = <0x20000000 0x04000000>; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun clocks { 55*4882a593Smuzhiyun slow_xtal: slow_xtal { 56*4882a593Smuzhiyun compatible = "fixed-clock"; 57*4882a593Smuzhiyun #clock-cells = <0>; 58*4882a593Smuzhiyun clock-frequency = <0>; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun main_xtal: main_xtal { 62*4882a593Smuzhiyun compatible = "fixed-clock"; 63*4882a593Smuzhiyun #clock-cells = <0>; 64*4882a593Smuzhiyun clock-frequency = <0>; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun adc_op_clk: adc_op_clk{ 68*4882a593Smuzhiyun compatible = "fixed-clock"; 69*4882a593Smuzhiyun #clock-cells = <0>; 70*4882a593Smuzhiyun clock-frequency = <5000000>; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun sram0: sram@2ff000 { 75*4882a593Smuzhiyun compatible = "mmio-sram"; 76*4882a593Smuzhiyun reg = <0x002ff000 0x2000>; 77*4882a593Smuzhiyun #address-cells = <1>; 78*4882a593Smuzhiyun #size-cells = <1>; 79*4882a593Smuzhiyun ranges = <0 0x002ff000 0x2000>; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun ahb { 83*4882a593Smuzhiyun compatible = "simple-bus"; 84*4882a593Smuzhiyun #address-cells = <1>; 85*4882a593Smuzhiyun #size-cells = <1>; 86*4882a593Smuzhiyun ranges; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun apb { 89*4882a593Smuzhiyun compatible = "simple-bus"; 90*4882a593Smuzhiyun #address-cells = <1>; 91*4882a593Smuzhiyun #size-cells = <1>; 92*4882a593Smuzhiyun ranges; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun aic: interrupt-controller@fffff000 { 95*4882a593Smuzhiyun #interrupt-cells = <3>; 96*4882a593Smuzhiyun compatible = "atmel,at91rm9200-aic"; 97*4882a593Smuzhiyun interrupt-controller; 98*4882a593Smuzhiyun reg = <0xfffff000 0x200>; 99*4882a593Smuzhiyun atmel,external-irqs = <29 30 31>; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun ramc0: ramc@ffffea00 { 103*4882a593Smuzhiyun compatible = "atmel,at91sam9260-sdramc"; 104*4882a593Smuzhiyun reg = <0xffffea00 0x200>; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun smc: smc@ffffec00 { 108*4882a593Smuzhiyun compatible = "atmel,at91sam9260-smc", "syscon"; 109*4882a593Smuzhiyun reg = <0xffffec00 0x200>; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun matrix: matrix@ffffee00 { 113*4882a593Smuzhiyun compatible = "atmel,at91sam9260-matrix", "syscon"; 114*4882a593Smuzhiyun reg = <0xffffee00 0x200>; 115*4882a593Smuzhiyun }; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun pmc: pmc@fffffc00 { 118*4882a593Smuzhiyun compatible = "atmel,at91sam9260-pmc", "syscon"; 119*4882a593Smuzhiyun reg = <0xfffffc00 0x100>; 120*4882a593Smuzhiyun interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 121*4882a593Smuzhiyun #clock-cells = <2>; 122*4882a593Smuzhiyun clocks = <&slow_xtal>, <&main_xtal>; 123*4882a593Smuzhiyun clock-names = "slow_xtal", "main_xtal"; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun rstc@fffffd00 { 127*4882a593Smuzhiyun compatible = "atmel,at91sam9260-rstc"; 128*4882a593Smuzhiyun reg = <0xfffffd00 0x10>; 129*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; 130*4882a593Smuzhiyun }; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun shdwc@fffffd10 { 133*4882a593Smuzhiyun compatible = "atmel,at91sam9260-shdwc"; 134*4882a593Smuzhiyun reg = <0xfffffd10 0x10>; 135*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun pit: timer@fffffd30 { 139*4882a593Smuzhiyun compatible = "atmel,at91sam9260-pit"; 140*4882a593Smuzhiyun reg = <0xfffffd30 0xf>; 141*4882a593Smuzhiyun interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 142*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 143*4882a593Smuzhiyun }; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun tcb0: timer@fffa0000 { 146*4882a593Smuzhiyun compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; 147*4882a593Smuzhiyun #address-cells = <1>; 148*4882a593Smuzhiyun #size-cells = <0>; 149*4882a593Smuzhiyun reg = <0xfffa0000 0x100>; 150*4882a593Smuzhiyun interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 151*4882a593Smuzhiyun 18 IRQ_TYPE_LEVEL_HIGH 0 152*4882a593Smuzhiyun 19 IRQ_TYPE_LEVEL_HIGH 0>; 153*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 19>, <&pmc PMC_TYPE_CORE PMC_SLOW>; 154*4882a593Smuzhiyun clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; 155*4882a593Smuzhiyun }; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun tcb1: timer@fffdc000 { 158*4882a593Smuzhiyun compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; 159*4882a593Smuzhiyun #address-cells = <1>; 160*4882a593Smuzhiyun #size-cells = <0>; 161*4882a593Smuzhiyun reg = <0xfffdc000 0x100>; 162*4882a593Smuzhiyun interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0 163*4882a593Smuzhiyun 27 IRQ_TYPE_LEVEL_HIGH 0 164*4882a593Smuzhiyun 28 IRQ_TYPE_LEVEL_HIGH 0>; 165*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 28>, <&pmc PMC_TYPE_CORE PMC_SLOW>; 166*4882a593Smuzhiyun clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; 167*4882a593Smuzhiyun }; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun pinctrl@fffff400 { 170*4882a593Smuzhiyun #address-cells = <1>; 171*4882a593Smuzhiyun #size-cells = <1>; 172*4882a593Smuzhiyun compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; 173*4882a593Smuzhiyun ranges = <0xfffff400 0xfffff400 0x600>; 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun atmel,mux-mask = < 176*4882a593Smuzhiyun /* A B */ 177*4882a593Smuzhiyun 0xffffffff 0xffc00c3b /* pioA */ 178*4882a593Smuzhiyun 0xffffffff 0x7fff3ccf /* pioB */ 179*4882a593Smuzhiyun 0xffffffff 0x007fffff /* pioC */ 180*4882a593Smuzhiyun >; 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun /* shared pinctrl settings */ 183*4882a593Smuzhiyun dbgu { 184*4882a593Smuzhiyun pinctrl_dbgu: dbgu-0 { 185*4882a593Smuzhiyun atmel,pins = 186*4882a593Smuzhiyun <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP 187*4882a593Smuzhiyun AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; 188*4882a593Smuzhiyun }; 189*4882a593Smuzhiyun }; 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun usart0 { 192*4882a593Smuzhiyun pinctrl_usart0: usart0-0 { 193*4882a593Smuzhiyun atmel,pins = 194*4882a593Smuzhiyun <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP 195*4882a593Smuzhiyun AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; 196*4882a593Smuzhiyun }; 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun pinctrl_usart0_rts: usart0_rts-0 { 199*4882a593Smuzhiyun atmel,pins = 200*4882a593Smuzhiyun <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB26 periph A */ 201*4882a593Smuzhiyun }; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun pinctrl_usart0_cts: usart0_cts-0 { 204*4882a593Smuzhiyun atmel,pins = 205*4882a593Smuzhiyun <AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A */ 206*4882a593Smuzhiyun }; 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 { 209*4882a593Smuzhiyun atmel,pins = 210*4882a593Smuzhiyun <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A */ 211*4882a593Smuzhiyun AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB22 periph A */ 212*4882a593Smuzhiyun }; 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun pinctrl_usart0_dcd: usart0_dcd-0 { 215*4882a593Smuzhiyun atmel,pins = 216*4882a593Smuzhiyun <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB23 periph A */ 217*4882a593Smuzhiyun }; 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun pinctrl_usart0_ri: usart0_ri-0 { 220*4882a593Smuzhiyun atmel,pins = 221*4882a593Smuzhiyun <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB25 periph A */ 222*4882a593Smuzhiyun }; 223*4882a593Smuzhiyun }; 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun usart1 { 226*4882a593Smuzhiyun pinctrl_usart1: usart1-0 { 227*4882a593Smuzhiyun atmel,pins = 228*4882a593Smuzhiyun <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP 229*4882a593Smuzhiyun AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; 230*4882a593Smuzhiyun }; 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun pinctrl_usart1_rts: usart1_rts-0 { 233*4882a593Smuzhiyun atmel,pins = 234*4882a593Smuzhiyun <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB28 periph A */ 235*4882a593Smuzhiyun }; 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun pinctrl_usart1_cts: usart1_cts-0 { 238*4882a593Smuzhiyun atmel,pins = 239*4882a593Smuzhiyun <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB29 periph A */ 240*4882a593Smuzhiyun }; 241*4882a593Smuzhiyun }; 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun usart2 { 244*4882a593Smuzhiyun pinctrl_usart2: usart2-0 { 245*4882a593Smuzhiyun atmel,pins = 246*4882a593Smuzhiyun <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP 247*4882a593Smuzhiyun AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; 248*4882a593Smuzhiyun }; 249*4882a593Smuzhiyun 250*4882a593Smuzhiyun pinctrl_usart2_rts: usart2_rts-0 { 251*4882a593Smuzhiyun atmel,pins = 252*4882a593Smuzhiyun <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA4 periph A */ 253*4882a593Smuzhiyun }; 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun pinctrl_usart2_cts: usart2_cts-0 { 256*4882a593Smuzhiyun atmel,pins = 257*4882a593Smuzhiyun <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA5 periph A */ 258*4882a593Smuzhiyun }; 259*4882a593Smuzhiyun }; 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun usart3 { 262*4882a593Smuzhiyun pinctrl_usart3: usart3-0 { 263*4882a593Smuzhiyun atmel,pins = 264*4882a593Smuzhiyun <AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP 265*4882a593Smuzhiyun AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; 266*4882a593Smuzhiyun }; 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun pinctrl_usart3_rts: usart3_rts-0 { 269*4882a593Smuzhiyun atmel,pins = 270*4882a593Smuzhiyun <AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; 271*4882a593Smuzhiyun }; 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun pinctrl_usart3_cts: usart3_cts-0 { 274*4882a593Smuzhiyun atmel,pins = 275*4882a593Smuzhiyun <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; 276*4882a593Smuzhiyun }; 277*4882a593Smuzhiyun }; 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun uart0 { 280*4882a593Smuzhiyun pinctrl_uart0: uart0-0 { 281*4882a593Smuzhiyun atmel,pins = 282*4882a593Smuzhiyun <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP 283*4882a593Smuzhiyun AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; 284*4882a593Smuzhiyun }; 285*4882a593Smuzhiyun }; 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun uart1 { 288*4882a593Smuzhiyun pinctrl_uart1: uart1-0 { 289*4882a593Smuzhiyun atmel,pins = 290*4882a593Smuzhiyun <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP 291*4882a593Smuzhiyun AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; 292*4882a593Smuzhiyun }; 293*4882a593Smuzhiyun }; 294*4882a593Smuzhiyun 295*4882a593Smuzhiyun nand { 296*4882a593Smuzhiyun pinctrl_nand_rb: nand-rb-0 { 297*4882a593Smuzhiyun atmel,pins = 298*4882a593Smuzhiyun <AT91_PIOC 13 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; 299*4882a593Smuzhiyun }; 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun pinctrl_nand_cs: nand-cs-0 { 302*4882a593Smuzhiyun atmel,pins = 303*4882a593Smuzhiyun <AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; 304*4882a593Smuzhiyun }; 305*4882a593Smuzhiyun }; 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun macb { 308*4882a593Smuzhiyun pinctrl_macb_rmii: macb_rmii-0 { 309*4882a593Smuzhiyun atmel,pins = 310*4882a593Smuzhiyun <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */ 311*4882a593Smuzhiyun AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */ 312*4882a593Smuzhiyun AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */ 313*4882a593Smuzhiyun AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */ 314*4882a593Smuzhiyun AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA16 periph A */ 315*4882a593Smuzhiyun AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */ 316*4882a593Smuzhiyun AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA18 periph A */ 317*4882a593Smuzhiyun AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA19 periph A */ 318*4882a593Smuzhiyun AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA20 periph A */ 319*4882a593Smuzhiyun AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */ 320*4882a593Smuzhiyun }; 321*4882a593Smuzhiyun 322*4882a593Smuzhiyun pinctrl_macb_rmii_mii: macb_rmii_mii-0 { 323*4882a593Smuzhiyun atmel,pins = 324*4882a593Smuzhiyun <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B */ 325*4882a593Smuzhiyun AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA23 periph B */ 326*4882a593Smuzhiyun AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA24 periph B */ 327*4882a593Smuzhiyun AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */ 328*4882a593Smuzhiyun AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA26 periph B */ 329*4882a593Smuzhiyun AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ 330*4882a593Smuzhiyun AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ 331*4882a593Smuzhiyun AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */ 332*4882a593Smuzhiyun }; 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun pinctrl_macb_rmii_mii_alt: macb_rmii_mii-1 { 335*4882a593Smuzhiyun atmel,pins = 336*4882a593Smuzhiyun <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA10 periph B */ 337*4882a593Smuzhiyun AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA11 periph B */ 338*4882a593Smuzhiyun AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA22 periph B */ 339*4882a593Smuzhiyun AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA25 periph B */ 340*4882a593Smuzhiyun AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA26 periph B */ 341*4882a593Smuzhiyun AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */ 342*4882a593Smuzhiyun AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */ 343*4882a593Smuzhiyun AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */ 344*4882a593Smuzhiyun }; 345*4882a593Smuzhiyun }; 346*4882a593Smuzhiyun 347*4882a593Smuzhiyun mmc0 { 348*4882a593Smuzhiyun pinctrl_mmc0_clk: mmc0_clk-0 { 349*4882a593Smuzhiyun atmel,pins = 350*4882a593Smuzhiyun <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA8 periph A */ 351*4882a593Smuzhiyun }; 352*4882a593Smuzhiyun 353*4882a593Smuzhiyun pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { 354*4882a593Smuzhiyun atmel,pins = 355*4882a593Smuzhiyun <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */ 356*4882a593Smuzhiyun AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA6 periph A with pullup */ 357*4882a593Smuzhiyun }; 358*4882a593Smuzhiyun 359*4882a593Smuzhiyun pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { 360*4882a593Smuzhiyun atmel,pins = 361*4882a593Smuzhiyun <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA9 periph A with pullup */ 362*4882a593Smuzhiyun AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA10 periph A with pullup */ 363*4882a593Smuzhiyun AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA11 periph A with pullup */ 364*4882a593Smuzhiyun }; 365*4882a593Smuzhiyun 366*4882a593Smuzhiyun pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { 367*4882a593Smuzhiyun atmel,pins = 368*4882a593Smuzhiyun <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA1 periph B with pullup */ 369*4882a593Smuzhiyun AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA0 periph B with pullup */ 370*4882a593Smuzhiyun }; 371*4882a593Smuzhiyun 372*4882a593Smuzhiyun pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { 373*4882a593Smuzhiyun atmel,pins = 374*4882a593Smuzhiyun <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA5 periph B with pullup */ 375*4882a593Smuzhiyun AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA4 periph B with pullup */ 376*4882a593Smuzhiyun AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA3 periph B with pullup */ 377*4882a593Smuzhiyun }; 378*4882a593Smuzhiyun }; 379*4882a593Smuzhiyun 380*4882a593Smuzhiyun ssc0 { 381*4882a593Smuzhiyun pinctrl_ssc0_tx: ssc0_tx-0 { 382*4882a593Smuzhiyun atmel,pins = 383*4882a593Smuzhiyun <AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */ 384*4882a593Smuzhiyun AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB17 periph A */ 385*4882a593Smuzhiyun AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */ 386*4882a593Smuzhiyun }; 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun pinctrl_ssc0_rx: ssc0_rx-0 { 389*4882a593Smuzhiyun atmel,pins = 390*4882a593Smuzhiyun <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB19 periph A */ 391*4882a593Smuzhiyun AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB20 periph A */ 392*4882a593Smuzhiyun AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB21 periph A */ 393*4882a593Smuzhiyun }; 394*4882a593Smuzhiyun }; 395*4882a593Smuzhiyun 396*4882a593Smuzhiyun spi0 { 397*4882a593Smuzhiyun pinctrl_spi0: spi0-0 { 398*4882a593Smuzhiyun atmel,pins = 399*4882a593Smuzhiyun <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A SPI0_MISO pin */ 400*4882a593Smuzhiyun AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A SPI0_MOSI pin */ 401*4882a593Smuzhiyun AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A SPI0_SPCK pin */ 402*4882a593Smuzhiyun }; 403*4882a593Smuzhiyun }; 404*4882a593Smuzhiyun 405*4882a593Smuzhiyun spi1 { 406*4882a593Smuzhiyun pinctrl_spi1: spi1-0 { 407*4882a593Smuzhiyun atmel,pins = 408*4882a593Smuzhiyun <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI1_MISO pin */ 409*4882a593Smuzhiyun AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A SPI1_MOSI pin */ 410*4882a593Smuzhiyun AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A SPI1_SPCK pin */ 411*4882a593Smuzhiyun }; 412*4882a593Smuzhiyun }; 413*4882a593Smuzhiyun 414*4882a593Smuzhiyun i2c_gpio0 { 415*4882a593Smuzhiyun pinctrl_i2c_gpio0: i2c_gpio0-0 { 416*4882a593Smuzhiyun atmel,pins = 417*4882a593Smuzhiyun <AT91_PIOA 23 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE 418*4882a593Smuzhiyun AT91_PIOA 24 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; 419*4882a593Smuzhiyun }; 420*4882a593Smuzhiyun }; 421*4882a593Smuzhiyun 422*4882a593Smuzhiyun tcb0 { 423*4882a593Smuzhiyun pinctrl_tcb0_tclk0: tcb0_tclk0-0 { 424*4882a593Smuzhiyun atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; 425*4882a593Smuzhiyun }; 426*4882a593Smuzhiyun 427*4882a593Smuzhiyun pinctrl_tcb0_tclk1: tcb0_tclk1-0 { 428*4882a593Smuzhiyun atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; 429*4882a593Smuzhiyun }; 430*4882a593Smuzhiyun 431*4882a593Smuzhiyun pinctrl_tcb0_tclk2: tcb0_tclk2-0 { 432*4882a593Smuzhiyun atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>; 433*4882a593Smuzhiyun }; 434*4882a593Smuzhiyun 435*4882a593Smuzhiyun pinctrl_tcb0_tioa0: tcb0_tioa0-0 { 436*4882a593Smuzhiyun atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; 437*4882a593Smuzhiyun }; 438*4882a593Smuzhiyun 439*4882a593Smuzhiyun pinctrl_tcb0_tioa1: tcb0_tioa1-0 { 440*4882a593Smuzhiyun atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; 441*4882a593Smuzhiyun }; 442*4882a593Smuzhiyun 443*4882a593Smuzhiyun pinctrl_tcb0_tioa2: tcb0_tioa2-0 { 444*4882a593Smuzhiyun atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; 445*4882a593Smuzhiyun }; 446*4882a593Smuzhiyun 447*4882a593Smuzhiyun pinctrl_tcb0_tiob0: tcb0_tiob0-0 { 448*4882a593Smuzhiyun atmel,pins = <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; 449*4882a593Smuzhiyun }; 450*4882a593Smuzhiyun 451*4882a593Smuzhiyun pinctrl_tcb0_tiob1: tcb0_tiob1-0 { 452*4882a593Smuzhiyun atmel,pins = <AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; 453*4882a593Smuzhiyun }; 454*4882a593Smuzhiyun 455*4882a593Smuzhiyun pinctrl_tcb0_tiob2: tcb0_tiob2-0 { 456*4882a593Smuzhiyun atmel,pins = <AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; 457*4882a593Smuzhiyun }; 458*4882a593Smuzhiyun }; 459*4882a593Smuzhiyun 460*4882a593Smuzhiyun tcb1 { 461*4882a593Smuzhiyun pinctrl_tcb1_tclk0: tcb1_tclk0-0 { 462*4882a593Smuzhiyun atmel,pins = <AT91_PIOB 16 AT91_PERIPH_B AT91_PINCTRL_NONE>; 463*4882a593Smuzhiyun }; 464*4882a593Smuzhiyun 465*4882a593Smuzhiyun pinctrl_tcb1_tclk1: tcb1_tclk1-0 { 466*4882a593Smuzhiyun atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; 467*4882a593Smuzhiyun }; 468*4882a593Smuzhiyun 469*4882a593Smuzhiyun pinctrl_tcb1_tclk2: tcb1_tclk2-0 { 470*4882a593Smuzhiyun atmel,pins = <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; 471*4882a593Smuzhiyun }; 472*4882a593Smuzhiyun 473*4882a593Smuzhiyun pinctrl_tcb1_tioa0: tcb1_tioa0-0 { 474*4882a593Smuzhiyun atmel,pins = <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; 475*4882a593Smuzhiyun }; 476*4882a593Smuzhiyun 477*4882a593Smuzhiyun pinctrl_tcb1_tioa1: tcb1_tioa1-0 { 478*4882a593Smuzhiyun atmel,pins = <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; 479*4882a593Smuzhiyun }; 480*4882a593Smuzhiyun 481*4882a593Smuzhiyun pinctrl_tcb1_tioa2: tcb1_tioa2-0 { 482*4882a593Smuzhiyun atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; 483*4882a593Smuzhiyun }; 484*4882a593Smuzhiyun 485*4882a593Smuzhiyun pinctrl_tcb1_tiob0: tcb1_tiob0-0 { 486*4882a593Smuzhiyun atmel,pins = <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; 487*4882a593Smuzhiyun }; 488*4882a593Smuzhiyun 489*4882a593Smuzhiyun pinctrl_tcb1_tiob1: tcb1_tiob1-0 { 490*4882a593Smuzhiyun atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>; 491*4882a593Smuzhiyun }; 492*4882a593Smuzhiyun 493*4882a593Smuzhiyun pinctrl_tcb1_tiob2: tcb1_tiob2-0 { 494*4882a593Smuzhiyun atmel,pins = <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; 495*4882a593Smuzhiyun }; 496*4882a593Smuzhiyun }; 497*4882a593Smuzhiyun 498*4882a593Smuzhiyun pioA: gpio@fffff400 { 499*4882a593Smuzhiyun compatible = "atmel,at91rm9200-gpio"; 500*4882a593Smuzhiyun reg = <0xfffff400 0x200>; 501*4882a593Smuzhiyun interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; 502*4882a593Smuzhiyun #gpio-cells = <2>; 503*4882a593Smuzhiyun gpio-controller; 504*4882a593Smuzhiyun interrupt-controller; 505*4882a593Smuzhiyun #interrupt-cells = <2>; 506*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; 507*4882a593Smuzhiyun }; 508*4882a593Smuzhiyun 509*4882a593Smuzhiyun pioB: gpio@fffff600 { 510*4882a593Smuzhiyun compatible = "atmel,at91rm9200-gpio"; 511*4882a593Smuzhiyun reg = <0xfffff600 0x200>; 512*4882a593Smuzhiyun interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; 513*4882a593Smuzhiyun #gpio-cells = <2>; 514*4882a593Smuzhiyun gpio-controller; 515*4882a593Smuzhiyun interrupt-controller; 516*4882a593Smuzhiyun #interrupt-cells = <2>; 517*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; 518*4882a593Smuzhiyun }; 519*4882a593Smuzhiyun 520*4882a593Smuzhiyun pioC: gpio@fffff800 { 521*4882a593Smuzhiyun compatible = "atmel,at91rm9200-gpio"; 522*4882a593Smuzhiyun reg = <0xfffff800 0x200>; 523*4882a593Smuzhiyun interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; 524*4882a593Smuzhiyun #gpio-cells = <2>; 525*4882a593Smuzhiyun gpio-controller; 526*4882a593Smuzhiyun interrupt-controller; 527*4882a593Smuzhiyun #interrupt-cells = <2>; 528*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; 529*4882a593Smuzhiyun }; 530*4882a593Smuzhiyun }; 531*4882a593Smuzhiyun 532*4882a593Smuzhiyun dbgu: serial@fffff200 { 533*4882a593Smuzhiyun compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 534*4882a593Smuzhiyun reg = <0xfffff200 0x200>; 535*4882a593Smuzhiyun interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 536*4882a593Smuzhiyun pinctrl-names = "default"; 537*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_dbgu>; 538*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 539*4882a593Smuzhiyun clock-names = "usart"; 540*4882a593Smuzhiyun status = "disabled"; 541*4882a593Smuzhiyun }; 542*4882a593Smuzhiyun 543*4882a593Smuzhiyun usart0: serial@fffb0000 { 544*4882a593Smuzhiyun compatible = "atmel,at91sam9260-usart"; 545*4882a593Smuzhiyun reg = <0xfffb0000 0x200>; 546*4882a593Smuzhiyun interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; 547*4882a593Smuzhiyun atmel,use-dma-rx; 548*4882a593Smuzhiyun atmel,use-dma-tx; 549*4882a593Smuzhiyun pinctrl-names = "default"; 550*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usart0>; 551*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 552*4882a593Smuzhiyun clock-names = "usart"; 553*4882a593Smuzhiyun status = "disabled"; 554*4882a593Smuzhiyun }; 555*4882a593Smuzhiyun 556*4882a593Smuzhiyun usart1: serial@fffb4000 { 557*4882a593Smuzhiyun compatible = "atmel,at91sam9260-usart"; 558*4882a593Smuzhiyun reg = <0xfffb4000 0x200>; 559*4882a593Smuzhiyun interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; 560*4882a593Smuzhiyun atmel,use-dma-rx; 561*4882a593Smuzhiyun atmel,use-dma-tx; 562*4882a593Smuzhiyun pinctrl-names = "default"; 563*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usart1>; 564*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 565*4882a593Smuzhiyun clock-names = "usart"; 566*4882a593Smuzhiyun status = "disabled"; 567*4882a593Smuzhiyun }; 568*4882a593Smuzhiyun 569*4882a593Smuzhiyun usart2: serial@fffb8000 { 570*4882a593Smuzhiyun compatible = "atmel,at91sam9260-usart"; 571*4882a593Smuzhiyun reg = <0xfffb8000 0x200>; 572*4882a593Smuzhiyun interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; 573*4882a593Smuzhiyun atmel,use-dma-rx; 574*4882a593Smuzhiyun atmel,use-dma-tx; 575*4882a593Smuzhiyun pinctrl-names = "default"; 576*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usart2>; 577*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 578*4882a593Smuzhiyun clock-names = "usart"; 579*4882a593Smuzhiyun status = "disabled"; 580*4882a593Smuzhiyun }; 581*4882a593Smuzhiyun 582*4882a593Smuzhiyun usart3: serial@fffd0000 { 583*4882a593Smuzhiyun compatible = "atmel,at91sam9260-usart"; 584*4882a593Smuzhiyun reg = <0xfffd0000 0x200>; 585*4882a593Smuzhiyun interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>; 586*4882a593Smuzhiyun atmel,use-dma-rx; 587*4882a593Smuzhiyun atmel,use-dma-tx; 588*4882a593Smuzhiyun pinctrl-names = "default"; 589*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_usart3>; 590*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 591*4882a593Smuzhiyun clock-names = "usart"; 592*4882a593Smuzhiyun status = "disabled"; 593*4882a593Smuzhiyun }; 594*4882a593Smuzhiyun 595*4882a593Smuzhiyun uart0: serial@fffd4000 { 596*4882a593Smuzhiyun compatible = "atmel,at91sam9260-usart"; 597*4882a593Smuzhiyun reg = <0xfffd4000 0x200>; 598*4882a593Smuzhiyun interrupts = <24 IRQ_TYPE_LEVEL_HIGH 5>; 599*4882a593Smuzhiyun atmel,use-dma-rx; 600*4882a593Smuzhiyun atmel,use-dma-tx; 601*4882a593Smuzhiyun pinctrl-names = "default"; 602*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart0>; 603*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; 604*4882a593Smuzhiyun clock-names = "usart"; 605*4882a593Smuzhiyun status = "disabled"; 606*4882a593Smuzhiyun }; 607*4882a593Smuzhiyun 608*4882a593Smuzhiyun uart1: serial@fffd8000 { 609*4882a593Smuzhiyun compatible = "atmel,at91sam9260-usart"; 610*4882a593Smuzhiyun reg = <0xfffd8000 0x200>; 611*4882a593Smuzhiyun interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>; 612*4882a593Smuzhiyun atmel,use-dma-rx; 613*4882a593Smuzhiyun atmel,use-dma-tx; 614*4882a593Smuzhiyun pinctrl-names = "default"; 615*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart1>; 616*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; 617*4882a593Smuzhiyun clock-names = "usart"; 618*4882a593Smuzhiyun status = "disabled"; 619*4882a593Smuzhiyun }; 620*4882a593Smuzhiyun 621*4882a593Smuzhiyun macb0: ethernet@fffc4000 { 622*4882a593Smuzhiyun compatible = "cdns,at91sam9260-macb", "cdns,macb"; 623*4882a593Smuzhiyun reg = <0xfffc4000 0x100>; 624*4882a593Smuzhiyun interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; 625*4882a593Smuzhiyun pinctrl-names = "default"; 626*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_macb_rmii>; 627*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_PERIPHERAL 21>; 628*4882a593Smuzhiyun clock-names = "hclk", "pclk"; 629*4882a593Smuzhiyun status = "disabled"; 630*4882a593Smuzhiyun }; 631*4882a593Smuzhiyun 632*4882a593Smuzhiyun usb1: gadget@fffa4000 { 633*4882a593Smuzhiyun compatible = "atmel,at91sam9260-udc"; 634*4882a593Smuzhiyun reg = <0xfffa4000 0x4000>; 635*4882a593Smuzhiyun interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>; 636*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 10>, <&pmc PMC_TYPE_SYSTEM 7>; 637*4882a593Smuzhiyun clock-names = "pclk", "hclk"; 638*4882a593Smuzhiyun status = "disabled"; 639*4882a593Smuzhiyun }; 640*4882a593Smuzhiyun 641*4882a593Smuzhiyun i2c0: i2c@fffac000 { 642*4882a593Smuzhiyun compatible = "atmel,at91sam9260-i2c"; 643*4882a593Smuzhiyun reg = <0xfffac000 0x100>; 644*4882a593Smuzhiyun interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; 645*4882a593Smuzhiyun #address-cells = <1>; 646*4882a593Smuzhiyun #size-cells = <0>; 647*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 648*4882a593Smuzhiyun status = "disabled"; 649*4882a593Smuzhiyun }; 650*4882a593Smuzhiyun 651*4882a593Smuzhiyun mmc0: mmc@fffa8000 { 652*4882a593Smuzhiyun compatible = "atmel,hsmci"; 653*4882a593Smuzhiyun reg = <0xfffa8000 0x600>; 654*4882a593Smuzhiyun interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; 655*4882a593Smuzhiyun #address-cells = <1>; 656*4882a593Smuzhiyun #size-cells = <0>; 657*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 658*4882a593Smuzhiyun clock-names = "mci_clk"; 659*4882a593Smuzhiyun status = "disabled"; 660*4882a593Smuzhiyun }; 661*4882a593Smuzhiyun 662*4882a593Smuzhiyun ssc0: ssc@fffbc000 { 663*4882a593Smuzhiyun compatible = "atmel,at91rm9200-ssc"; 664*4882a593Smuzhiyun reg = <0xfffbc000 0x4000>; 665*4882a593Smuzhiyun interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; 666*4882a593Smuzhiyun pinctrl-names = "default"; 667*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; 668*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 669*4882a593Smuzhiyun clock-names = "pclk"; 670*4882a593Smuzhiyun status = "disabled"; 671*4882a593Smuzhiyun }; 672*4882a593Smuzhiyun 673*4882a593Smuzhiyun spi0: spi@fffc8000 { 674*4882a593Smuzhiyun #address-cells = <1>; 675*4882a593Smuzhiyun #size-cells = <0>; 676*4882a593Smuzhiyun compatible = "atmel,at91rm9200-spi"; 677*4882a593Smuzhiyun reg = <0xfffc8000 0x200>; 678*4882a593Smuzhiyun interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; 679*4882a593Smuzhiyun pinctrl-names = "default"; 680*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_spi0>; 681*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; 682*4882a593Smuzhiyun clock-names = "spi_clk"; 683*4882a593Smuzhiyun status = "disabled"; 684*4882a593Smuzhiyun }; 685*4882a593Smuzhiyun 686*4882a593Smuzhiyun spi1: spi@fffcc000 { 687*4882a593Smuzhiyun #address-cells = <1>; 688*4882a593Smuzhiyun #size-cells = <0>; 689*4882a593Smuzhiyun compatible = "atmel,at91rm9200-spi"; 690*4882a593Smuzhiyun reg = <0xfffcc000 0x200>; 691*4882a593Smuzhiyun interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; 692*4882a593Smuzhiyun pinctrl-names = "default"; 693*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_spi1>; 694*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 695*4882a593Smuzhiyun clock-names = "spi_clk"; 696*4882a593Smuzhiyun status = "disabled"; 697*4882a593Smuzhiyun }; 698*4882a593Smuzhiyun 699*4882a593Smuzhiyun adc0: adc@fffe0000 { 700*4882a593Smuzhiyun #address-cells = <1>; 701*4882a593Smuzhiyun #size-cells = <0>; 702*4882a593Smuzhiyun compatible = "atmel,at91sam9260-adc"; 703*4882a593Smuzhiyun reg = <0xfffe0000 0x100>; 704*4882a593Smuzhiyun interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>; 705*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&adc_op_clk>; 706*4882a593Smuzhiyun clock-names = "adc_clk", "adc_op_clk"; 707*4882a593Smuzhiyun atmel,adc-use-external-triggers; 708*4882a593Smuzhiyun atmel,adc-channels-used = <0xf>; 709*4882a593Smuzhiyun atmel,adc-vref = <3300>; 710*4882a593Smuzhiyun atmel,adc-startup-time = <15>; 711*4882a593Smuzhiyun atmel,adc-res = <8 10>; 712*4882a593Smuzhiyun atmel,adc-res-names = "lowres", "highres"; 713*4882a593Smuzhiyun atmel,adc-use-res = "highres"; 714*4882a593Smuzhiyun 715*4882a593Smuzhiyun trigger0 { 716*4882a593Smuzhiyun trigger-name = "timer-counter-0"; 717*4882a593Smuzhiyun trigger-value = <0x1>; 718*4882a593Smuzhiyun }; 719*4882a593Smuzhiyun trigger1 { 720*4882a593Smuzhiyun trigger-name = "timer-counter-1"; 721*4882a593Smuzhiyun trigger-value = <0x3>; 722*4882a593Smuzhiyun }; 723*4882a593Smuzhiyun 724*4882a593Smuzhiyun trigger2 { 725*4882a593Smuzhiyun trigger-name = "timer-counter-2"; 726*4882a593Smuzhiyun trigger-value = <0x5>; 727*4882a593Smuzhiyun }; 728*4882a593Smuzhiyun 729*4882a593Smuzhiyun trigger3 { 730*4882a593Smuzhiyun trigger-name = "external"; 731*4882a593Smuzhiyun trigger-value = <0xd>; 732*4882a593Smuzhiyun trigger-external; 733*4882a593Smuzhiyun }; 734*4882a593Smuzhiyun }; 735*4882a593Smuzhiyun 736*4882a593Smuzhiyun rtc@fffffd20 { 737*4882a593Smuzhiyun compatible = "atmel,at91sam9260-rtt"; 738*4882a593Smuzhiyun reg = <0xfffffd20 0x10>; 739*4882a593Smuzhiyun interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 740*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; 741*4882a593Smuzhiyun status = "disabled"; 742*4882a593Smuzhiyun }; 743*4882a593Smuzhiyun 744*4882a593Smuzhiyun watchdog: watchdog@fffffd40 { 745*4882a593Smuzhiyun compatible = "atmel,at91sam9260-wdt"; 746*4882a593Smuzhiyun reg = <0xfffffd40 0x10>; 747*4882a593Smuzhiyun interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 748*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>; 749*4882a593Smuzhiyun atmel,watchdog-type = "hardware"; 750*4882a593Smuzhiyun atmel,reset-type = "all"; 751*4882a593Smuzhiyun atmel,dbg-halt; 752*4882a593Smuzhiyun status = "disabled"; 753*4882a593Smuzhiyun }; 754*4882a593Smuzhiyun 755*4882a593Smuzhiyun gpbr: syscon@fffffd50 { 756*4882a593Smuzhiyun compatible = "atmel,at91sam9260-gpbr", "syscon"; 757*4882a593Smuzhiyun reg = <0xfffffd50 0x10>; 758*4882a593Smuzhiyun status = "disabled"; 759*4882a593Smuzhiyun }; 760*4882a593Smuzhiyun }; 761*4882a593Smuzhiyun 762*4882a593Smuzhiyun usb0: ohci@500000 { 763*4882a593Smuzhiyun compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 764*4882a593Smuzhiyun reg = <0x00500000 0x100000>; 765*4882a593Smuzhiyun interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; 766*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_SYSTEM 6>; 767*4882a593Smuzhiyun clock-names = "ohci_clk", "hclk", "uhpck"; 768*4882a593Smuzhiyun status = "disabled"; 769*4882a593Smuzhiyun }; 770*4882a593Smuzhiyun 771*4882a593Smuzhiyun ebi: ebi@10000000 { 772*4882a593Smuzhiyun compatible = "atmel,at91sam9260-ebi"; 773*4882a593Smuzhiyun #address-cells = <2>; 774*4882a593Smuzhiyun #size-cells = <1>; 775*4882a593Smuzhiyun atmel,smc = <&smc>; 776*4882a593Smuzhiyun atmel,matrix = <&matrix>; 777*4882a593Smuzhiyun reg = <0x10000000 0x80000000>; 778*4882a593Smuzhiyun ranges = <0x0 0x0 0x10000000 0x10000000 779*4882a593Smuzhiyun 0x1 0x0 0x20000000 0x10000000 780*4882a593Smuzhiyun 0x2 0x0 0x30000000 0x10000000 781*4882a593Smuzhiyun 0x3 0x0 0x40000000 0x10000000 782*4882a593Smuzhiyun 0x4 0x0 0x50000000 0x10000000 783*4882a593Smuzhiyun 0x5 0x0 0x60000000 0x10000000 784*4882a593Smuzhiyun 0x6 0x0 0x70000000 0x10000000 785*4882a593Smuzhiyun 0x7 0x0 0x80000000 0x10000000>; 786*4882a593Smuzhiyun clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 787*4882a593Smuzhiyun status = "disabled"; 788*4882a593Smuzhiyun 789*4882a593Smuzhiyun nand_controller: nand-controller { 790*4882a593Smuzhiyun compatible = "atmel,at91sam9260-nand-controller"; 791*4882a593Smuzhiyun #address-cells = <2>; 792*4882a593Smuzhiyun #size-cells = <1>; 793*4882a593Smuzhiyun ranges; 794*4882a593Smuzhiyun status = "disabled"; 795*4882a593Smuzhiyun }; 796*4882a593Smuzhiyun }; 797*4882a593Smuzhiyun }; 798*4882a593Smuzhiyun 799*4882a593Smuzhiyun i2c_gpio0: i2c-gpio-0 { 800*4882a593Smuzhiyun compatible = "i2c-gpio"; 801*4882a593Smuzhiyun gpios = <&pioA 23 GPIO_ACTIVE_HIGH /* sda */ 802*4882a593Smuzhiyun &pioA 24 GPIO_ACTIVE_HIGH /* scl */ 803*4882a593Smuzhiyun >; 804*4882a593Smuzhiyun i2c-gpio,sda-open-drain; 805*4882a593Smuzhiyun i2c-gpio,scl-open-drain; 806*4882a593Smuzhiyun i2c-gpio,delay-us = <2>; /* ~100 kHz */ 807*4882a593Smuzhiyun #address-cells = <1>; 808*4882a593Smuzhiyun #size-cells = <0>; 809*4882a593Smuzhiyun pinctrl-names = "default"; 810*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c_gpio0>; 811*4882a593Smuzhiyun status = "disabled"; 812*4882a593Smuzhiyun }; 813*4882a593Smuzhiyun}; 814