xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * at91-sama5d27_wlsom1.dtsi - Device Tree file for SAMA5D27 WLSOM1
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Nicolas Ferre <nicolas.ferre@microcihp.com>
8*4882a593Smuzhiyun * Author: Eugen Hristev <eugen.hristev@microcihp.com>
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun#include "sama5d2.dtsi"
11*4882a593Smuzhiyun#include "sama5d2-pinfunc.h"
12*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
13*4882a593Smuzhiyun#include <dt-bindings/mfd/atmel-flexcom.h>
14*4882a593Smuzhiyun#include <dt-bindings/pinctrl/at91.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun/ {
17*4882a593Smuzhiyun	model = "Microchip SAMA5D27 WLSOM1";
18*4882a593Smuzhiyun	compatible = "microchip,sama5d27-wlsom1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5";
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun	aliases {
21*4882a593Smuzhiyun		i2c0 = &i2c0;
22*4882a593Smuzhiyun	};
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun	clocks {
25*4882a593Smuzhiyun		slow_xtal {
26*4882a593Smuzhiyun			clock-frequency = <32768>;
27*4882a593Smuzhiyun		};
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun		main_xtal {
30*4882a593Smuzhiyun			clock-frequency = <24000000>;
31*4882a593Smuzhiyun		};
32*4882a593Smuzhiyun	};
33*4882a593Smuzhiyun};
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun&flx1 {
36*4882a593Smuzhiyun	atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun	uart6: serial@200 {
39*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_flx1_default>;
40*4882a593Smuzhiyun		pinctrl-names = "default";
41*4882a593Smuzhiyun	};
42*4882a593Smuzhiyun};
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun&i2c0 {
45*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c0_default>;
46*4882a593Smuzhiyun	pinctrl-names = "default";
47*4882a593Smuzhiyun	status = "okay";
48*4882a593Smuzhiyun};
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun&i2c1 {
51*4882a593Smuzhiyun	dmas = <0>, <0>;
52*4882a593Smuzhiyun	pinctrl-names = "default";
53*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_i2c1_default>;
54*4882a593Smuzhiyun	status = "okay";
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun	mcp16502@5b {
57*4882a593Smuzhiyun		compatible = "microchip,mcp16502";
58*4882a593Smuzhiyun		reg = <0x5b>;
59*4882a593Smuzhiyun		status = "okay";
60*4882a593Smuzhiyun		lpm-gpios = <&pioBU 0 GPIO_ACTIVE_LOW>;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun		regulators {
63*4882a593Smuzhiyun			vdd_3v3: VDD_IO {
64*4882a593Smuzhiyun				regulator-name = "VDD_IO";
65*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
66*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
67*4882a593Smuzhiyun				regulator-initial-mode = <2>;
68*4882a593Smuzhiyun				regulator-allowed-modes = <2>, <4>;
69*4882a593Smuzhiyun				regulator-always-on;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun				regulator-state-standby {
72*4882a593Smuzhiyun					regulator-on-in-suspend;
73*4882a593Smuzhiyun					regulator-mode = <4>;
74*4882a593Smuzhiyun				};
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun				regulator-state-mem {
77*4882a593Smuzhiyun					regulator-off-in-suspend;
78*4882a593Smuzhiyun					regulator-mode = <4>;
79*4882a593Smuzhiyun				};
80*4882a593Smuzhiyun			};
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun			vddio_ddr: VDD_DDR {
83*4882a593Smuzhiyun				regulator-name = "VDD_DDR";
84*4882a593Smuzhiyun				regulator-min-microvolt = <1200000>;
85*4882a593Smuzhiyun				regulator-max-microvolt = <1200000>;
86*4882a593Smuzhiyun				regulator-initial-mode = <2>;
87*4882a593Smuzhiyun				regulator-allowed-modes = <2>, <4>;
88*4882a593Smuzhiyun				regulator-always-on;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun				regulator-state-standby {
91*4882a593Smuzhiyun					regulator-on-in-suspend;
92*4882a593Smuzhiyun					regulator-suspend-microvolt = <1200000>;
93*4882a593Smuzhiyun					regulator-changeable-in-suspend;
94*4882a593Smuzhiyun					regulator-mode = <4>;
95*4882a593Smuzhiyun				};
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun				regulator-state-mem {
98*4882a593Smuzhiyun					regulator-on-in-suspend;
99*4882a593Smuzhiyun					regulator-suspend-microvolt = <1200000>;
100*4882a593Smuzhiyun					regulator-changeable-in-suspend;
101*4882a593Smuzhiyun					regulator-mode = <4>;
102*4882a593Smuzhiyun				};
103*4882a593Smuzhiyun			};
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun			vdd_core: VDD_CORE {
106*4882a593Smuzhiyun				regulator-name = "VDD_CORE";
107*4882a593Smuzhiyun				regulator-min-microvolt = <1250000>;
108*4882a593Smuzhiyun				regulator-max-microvolt = <1250000>;
109*4882a593Smuzhiyun				regulator-initial-mode = <2>;
110*4882a593Smuzhiyun				regulator-allowed-modes = <2>, <4>;
111*4882a593Smuzhiyun				regulator-always-on;
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun				regulator-state-standby {
114*4882a593Smuzhiyun					regulator-on-in-suspend;
115*4882a593Smuzhiyun					regulator-mode = <4>;
116*4882a593Smuzhiyun				};
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun				regulator-state-mem {
119*4882a593Smuzhiyun					regulator-off-in-suspend;
120*4882a593Smuzhiyun					regulator-mode = <4>;
121*4882a593Smuzhiyun				};
122*4882a593Smuzhiyun			};
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun			vdd_ddr: VDD_OTHER {
125*4882a593Smuzhiyun				regulator-name = "VDD_OTHER";
126*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
127*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
128*4882a593Smuzhiyun				regulator-initial-mode = <2>;
129*4882a593Smuzhiyun				regulator-allowed-modes = <2>, <4>;
130*4882a593Smuzhiyun				regulator-always-on;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun				regulator-state-standby {
133*4882a593Smuzhiyun					regulator-on-in-suspend;
134*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
135*4882a593Smuzhiyun					regulator-changeable-in-suspend;
136*4882a593Smuzhiyun					regulator-mode = <4>;
137*4882a593Smuzhiyun				};
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun				regulator-state-mem {
140*4882a593Smuzhiyun					regulator-on-in-suspend;
141*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
142*4882a593Smuzhiyun					regulator-changeable-in-suspend;
143*4882a593Smuzhiyun					regulator-mode = <4>;
144*4882a593Smuzhiyun				};
145*4882a593Smuzhiyun			};
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun			LDO1 {
148*4882a593Smuzhiyun				regulator-name = "LDO1";
149*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
150*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
151*4882a593Smuzhiyun				regulator-always-on;
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun				regulator-state-standby {
154*4882a593Smuzhiyun					regulator-on-in-suspend;
155*4882a593Smuzhiyun				};
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun				regulator-state-mem {
158*4882a593Smuzhiyun					regulator-off-in-suspend;
159*4882a593Smuzhiyun				};
160*4882a593Smuzhiyun			};
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun			LDO2 {
163*4882a593Smuzhiyun				regulator-name = "LDO2";
164*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
165*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun				regulator-state-standby {
168*4882a593Smuzhiyun					regulator-on-in-suspend;
169*4882a593Smuzhiyun				};
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun				regulator-state-mem {
172*4882a593Smuzhiyun					regulator-off-in-suspend;
173*4882a593Smuzhiyun				};
174*4882a593Smuzhiyun			};
175*4882a593Smuzhiyun		};
176*4882a593Smuzhiyun	};
177*4882a593Smuzhiyun};
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun&macb0 {
180*4882a593Smuzhiyun	pinctrl-names = "default";
181*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_macb0_default>;
182*4882a593Smuzhiyun	phy-mode = "rmii";
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun	ethernet-phy@0 {
185*4882a593Smuzhiyun		reg = <0x0>;
186*4882a593Smuzhiyun		interrupt-parent = <&pioA>;
187*4882a593Smuzhiyun		interrupts = <PIN_PB24 IRQ_TYPE_LEVEL_LOW>;
188*4882a593Smuzhiyun		pinctrl-names = "default";
189*4882a593Smuzhiyun		pinctrl-0 = <&pinctrl_macb0_phy_irq>;
190*4882a593Smuzhiyun	};
191*4882a593Smuzhiyun};
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun&pmc {
194*4882a593Smuzhiyun	atmel,osc-bypass;
195*4882a593Smuzhiyun};
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun&qspi1 {
198*4882a593Smuzhiyun	pinctrl-names = "default";
199*4882a593Smuzhiyun	pinctrl-0 = <&pinctrl_qspi1_default>;
200*4882a593Smuzhiyun	status = "disabled";
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun	qspi1_flash: spi_flash@0 {
203*4882a593Smuzhiyun		#address-cells = <1>;
204*4882a593Smuzhiyun		#size-cells = <1>;
205*4882a593Smuzhiyun		compatible = "jedec,spi-nor";
206*4882a593Smuzhiyun		reg = <0>;
207*4882a593Smuzhiyun		spi-max-frequency = <80000000>;
208*4882a593Smuzhiyun		spi-rx-bus-width = <4>;
209*4882a593Smuzhiyun		spi-tx-bus-width = <4>;
210*4882a593Smuzhiyun		m25p,fast-read;
211*4882a593Smuzhiyun		status = "disabled";
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun		at91bootstrap@0 {
214*4882a593Smuzhiyun			label = "at91bootstrap";
215*4882a593Smuzhiyun			reg = <0x0 0x40000>;
216*4882a593Smuzhiyun		};
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun		bootloader@40000 {
219*4882a593Smuzhiyun			label = "bootloader";
220*4882a593Smuzhiyun			reg = <0x40000 0xc0000>;
221*4882a593Smuzhiyun		};
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun		bootloaderenvred@100000 {
224*4882a593Smuzhiyun			label = "bootloader env redundant";
225*4882a593Smuzhiyun			reg = <0x100000 0x40000>;
226*4882a593Smuzhiyun		};
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun		bootloaderenv@140000 {
229*4882a593Smuzhiyun			label = "bootloader env";
230*4882a593Smuzhiyun			reg = <0x140000 0x40000>;
231*4882a593Smuzhiyun		};
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun		dtb@180000 {
234*4882a593Smuzhiyun			label = "device tree";
235*4882a593Smuzhiyun			reg = <0x180000 0x80000>;
236*4882a593Smuzhiyun		};
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun		kernel@200000 {
239*4882a593Smuzhiyun			label = "kernel";
240*4882a593Smuzhiyun			reg = <0x200000 0x600000>;
241*4882a593Smuzhiyun		};
242*4882a593Smuzhiyun	};
243*4882a593Smuzhiyun};
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun&pioA {
246*4882a593Smuzhiyun	pinctrl_flx1_default: flx1_usart_default {
247*4882a593Smuzhiyun		pinmux = <PIN_PA24__FLEXCOM1_IO0>,
248*4882a593Smuzhiyun			 <PIN_PA23__FLEXCOM1_IO1>,
249*4882a593Smuzhiyun			 <PIN_PA25__FLEXCOM1_IO3>,
250*4882a593Smuzhiyun			 <PIN_PA26__FLEXCOM1_IO4>;
251*4882a593Smuzhiyun		bias-disable;
252*4882a593Smuzhiyun	};
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun	pinctrl_i2c0_default: i2c0_default {
255*4882a593Smuzhiyun		pinmux = <PIN_PD21__TWD0>,
256*4882a593Smuzhiyun			 <PIN_PD22__TWCK0>;
257*4882a593Smuzhiyun		bias-disable;
258*4882a593Smuzhiyun	};
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun	pinctrl_i2c1_default: i2c1_default {
261*4882a593Smuzhiyun		pinmux = <PIN_PD19__TWD1>,
262*4882a593Smuzhiyun			 <PIN_PD20__TWCK1>;
263*4882a593Smuzhiyun		bias-disable;
264*4882a593Smuzhiyun	};
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun	pinctrl_macb0_default: macb0_default {
267*4882a593Smuzhiyun		pinmux = <PIN_PB14__GTXCK>,
268*4882a593Smuzhiyun			 <PIN_PB15__GTXEN>,
269*4882a593Smuzhiyun			 <PIN_PB16__GRXDV>,
270*4882a593Smuzhiyun			 <PIN_PB17__GRXER>,
271*4882a593Smuzhiyun			 <PIN_PB18__GRX0>,
272*4882a593Smuzhiyun			 <PIN_PB19__GRX1>,
273*4882a593Smuzhiyun			 <PIN_PB20__GTX0>,
274*4882a593Smuzhiyun			 <PIN_PB21__GTX1>,
275*4882a593Smuzhiyun			 <PIN_PB22__GMDC>,
276*4882a593Smuzhiyun			 <PIN_PB23__GMDIO>;
277*4882a593Smuzhiyun		bias-disable;
278*4882a593Smuzhiyun	};
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun	pinctrl_macb0_phy_irq: macb0_phy_irq {
281*4882a593Smuzhiyun		pinmux = <PIN_PB24__GPIO>;
282*4882a593Smuzhiyun		bias-disable;
283*4882a593Smuzhiyun	};
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun	pinctrl_qspi1_default: qspi1_default {
286*4882a593Smuzhiyun		pinmux = <PIN_PB5__QSPI1_SCK>,
287*4882a593Smuzhiyun			 <PIN_PB6__QSPI1_CS>,
288*4882a593Smuzhiyun			 <PIN_PB7__QSPI1_IO0>,
289*4882a593Smuzhiyun			 <PIN_PB8__QSPI1_IO1>,
290*4882a593Smuzhiyun			 <PIN_PB9__QSPI1_IO2>,
291*4882a593Smuzhiyun			 <PIN_PB10__QSPI1_IO3>;
292*4882a593Smuzhiyun		bias-pull-up;
293*4882a593Smuzhiyun	};
294*4882a593Smuzhiyun};
295*4882a593Smuzhiyun
296