1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * at91-linea.dtsi - Device Tree Include file for the Axentia Linea Module. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2017 Axentia Technologies AB 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Peter Rosin <peda@axentia.se> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun#include "sama5d31.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun compatible = "axentia,linea", 14*4882a593Smuzhiyun "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun memory@20000000 { 17*4882a593Smuzhiyun reg = <0x20000000 0x4000000>; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun}; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun&slow_xtal { 22*4882a593Smuzhiyun clock-frequency = <32768>; 23*4882a593Smuzhiyun}; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun&main_xtal { 26*4882a593Smuzhiyun clock-frequency = <12000000>; 27*4882a593Smuzhiyun}; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun&tcb0 { 30*4882a593Smuzhiyun timer@0 { 31*4882a593Smuzhiyun compatible = "atmel,tcb-timer"; 32*4882a593Smuzhiyun reg = <0>; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun timer@1 { 36*4882a593Smuzhiyun compatible = "atmel,tcb-timer"; 37*4882a593Smuzhiyun reg = <1>; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun}; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun&i2c0 { 42*4882a593Smuzhiyun status = "okay"; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun eeprom@51 { 45*4882a593Smuzhiyun compatible = "st,24c64", "atmel,24c64"; 46*4882a593Smuzhiyun reg = <0x51>; 47*4882a593Smuzhiyun pagesize = <32>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun}; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun&ebi { 52*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_ebi_nand_addr>; 53*4882a593Smuzhiyun pinctrl-names = "default"; 54*4882a593Smuzhiyun status = "okay"; 55*4882a593Smuzhiyun}; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun&nand_controller { 59*4882a593Smuzhiyun status = "okay"; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun nand: nand@3 { 62*4882a593Smuzhiyun reg = <0x3 0x0 0x2>; 63*4882a593Smuzhiyun atmel,rb = <0>; 64*4882a593Smuzhiyun nand-bus-width = <8>; 65*4882a593Smuzhiyun nand-ecc-mode = "hw"; 66*4882a593Smuzhiyun nand-ecc-strength = <4>; 67*4882a593Smuzhiyun nand-ecc-step-size = <512>; 68*4882a593Smuzhiyun nand-on-flash-bbt; 69*4882a593Smuzhiyun label = "atmel_nand"; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun}; 72