1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree file for Marvell Armada XP Matrix board 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2013 Marvell 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Lior Amsalem <alior@marvell.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/dts-v1/; 11*4882a593Smuzhiyun#include "armada-xp-mv78460.dtsi" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/ { 14*4882a593Smuzhiyun model = "Marvell Armada XP Matrix Board"; 15*4882a593Smuzhiyun compatible = "marvell,axp-matrix", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun chosen { 18*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun memory@0 { 22*4882a593Smuzhiyun device_type = "memory"; 23*4882a593Smuzhiyun /* 24*4882a593Smuzhiyun * This board has 4 GB of RAM, but the last 256 MB of 25*4882a593Smuzhiyun * RAM are not usable due to the overlap with the MBus 26*4882a593Smuzhiyun * Window address range 27*4882a593Smuzhiyun */ 28*4882a593Smuzhiyun reg = <0 0x00000000 0 0xf0000000>; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun soc { 32*4882a593Smuzhiyun ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 33*4882a593Smuzhiyun MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 34*4882a593Smuzhiyun MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000 35*4882a593Smuzhiyun MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun internal-regs { 38*4882a593Smuzhiyun serial@12000 { 39*4882a593Smuzhiyun status = "okay"; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun serial@12100 { 42*4882a593Smuzhiyun status = "okay"; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun serial@12200 { 45*4882a593Smuzhiyun status = "okay"; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun serial@12300 { 48*4882a593Smuzhiyun status = "okay"; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun sata@a0000 { 52*4882a593Smuzhiyun nr-ports = <2>; 53*4882a593Smuzhiyun status = "okay"; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun ethernet@30000 { 57*4882a593Smuzhiyun status = "okay"; 58*4882a593Smuzhiyun phy-mode = "sgmii"; 59*4882a593Smuzhiyun fixed-link { 60*4882a593Smuzhiyun speed = <1000>; 61*4882a593Smuzhiyun full-duplex; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun usb@50000 { 66*4882a593Smuzhiyun status = "okay"; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun}; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun&pciec { 73*4882a593Smuzhiyun status = "okay"; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun pcie@1,0 { 76*4882a593Smuzhiyun /* Port 0, Lane 0 */ 77*4882a593Smuzhiyun status = "okay"; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun}; 80