1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree Include file for Marvell 98dx3336 family SoC 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2016 Allied Telesis Labs 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Contains definitions specific to the 98dx3236 SoC that are not 8*4882a593Smuzhiyun * common to all Armada XP SoCs. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun#include "armada-xp-98dx3236.dtsi" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/ { 14*4882a593Smuzhiyun model = "Marvell 98DX3336 SoC"; 15*4882a593Smuzhiyun compatible = "marvell,armadaxp-98dx3336", "marvell,armadaxp-98dx3236", "marvell,armada-370-xp"; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun cpus { 18*4882a593Smuzhiyun cpu@1 { 19*4882a593Smuzhiyun device_type = "cpu"; 20*4882a593Smuzhiyun compatible = "marvell,sheeva-v7"; 21*4882a593Smuzhiyun reg = <1>; 22*4882a593Smuzhiyun clocks = <&cpuclk 1>; 23*4882a593Smuzhiyun clock-latency = <1000000>; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun soc { 28*4882a593Smuzhiyun internal-regs { 29*4882a593Smuzhiyun resume@20980 { 30*4882a593Smuzhiyun compatible = "marvell,98dx3336-resume-ctrl"; 31*4882a593Smuzhiyun reg = <0x20980 0x10>; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun}; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun&pp0 { 38*4882a593Smuzhiyun compatible = "marvell,prestera-98dx3336", "marvell,prestera"; 39*4882a593Smuzhiyun}; 40