1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree Include file for Marvell Armada 395 SoC. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2016 Marvell 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Grzegorz Jaszczyk <jaz@semihalf.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun#include "armada-39x.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun compatible = "marvell,armada395", "marvell,armada390"; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun soc { 16*4882a593Smuzhiyun internal-regs { 17*4882a593Smuzhiyun pinctrl@18000 { 18*4882a593Smuzhiyun compatible = "marvell,mv88f6925-pinctrl"; 19*4882a593Smuzhiyun reg = <0x18000 0x20>; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun sata@a8000 { 23*4882a593Smuzhiyun compatible = "marvell,armada-380-ahci"; 24*4882a593Smuzhiyun reg = <0xa8000 0x2000>; 25*4882a593Smuzhiyun interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 26*4882a593Smuzhiyun clocks = <&gateclk 15>; 27*4882a593Smuzhiyun status = "disabled"; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun usb3@f0000 { 31*4882a593Smuzhiyun compatible = "marvell,armada-380-xhci"; 32*4882a593Smuzhiyun reg = <0xf0000 0x4000>,<0xf4000 0x4000>; 33*4882a593Smuzhiyun interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 34*4882a593Smuzhiyun clocks = <&gateclk 9>; 35*4882a593Smuzhiyun status = "disabled"; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun}; 40