1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree include file for SolidRun Clearfog 88F6828 based boards 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2015 Russell King 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include "armada-388.dtsi" 9*4882a593Smuzhiyun#include "armada-38x-solidrun-microsom.dtsi" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun aliases { 13*4882a593Smuzhiyun /* So that mvebu u-boot can update the MAC addresses */ 14*4882a593Smuzhiyun ethernet1 = ð0; 15*4882a593Smuzhiyun ethernet2 = ð1; 16*4882a593Smuzhiyun ethernet3 = ð2; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun chosen { 20*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun reg_3p3v: regulator-3p3v { 24*4882a593Smuzhiyun compatible = "regulator-fixed"; 25*4882a593Smuzhiyun regulator-name = "3P3V"; 26*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 27*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 28*4882a593Smuzhiyun regulator-always-on; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun soc { 32*4882a593Smuzhiyun internal-regs { 33*4882a593Smuzhiyun sata@a8000 { 34*4882a593Smuzhiyun /* pinctrl? */ 35*4882a593Smuzhiyun status = "okay"; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun sata@e0000 { 39*4882a593Smuzhiyun /* pinctrl? */ 40*4882a593Smuzhiyun status = "okay"; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun sdhci@d8000 { 44*4882a593Smuzhiyun bus-width = <4>; 45*4882a593Smuzhiyun cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; 46*4882a593Smuzhiyun no-1-8-v; 47*4882a593Smuzhiyun pinctrl-0 = <µsom_sdhci_pins 48*4882a593Smuzhiyun &clearfog_sdhci_cd_pins>; 49*4882a593Smuzhiyun pinctrl-names = "default"; 50*4882a593Smuzhiyun status = "okay"; 51*4882a593Smuzhiyun vmmc-supply = <®_3p3v>; 52*4882a593Smuzhiyun wp-inverted; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun usb@58000 { 56*4882a593Smuzhiyun /* CON3, nearest power. */ 57*4882a593Smuzhiyun status = "okay"; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun usb3@f8000 { 61*4882a593Smuzhiyun /* CON7 */ 62*4882a593Smuzhiyun status = "okay"; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun pcie { 67*4882a593Smuzhiyun status = "okay"; 68*4882a593Smuzhiyun /* 69*4882a593Smuzhiyun * The two PCIe units are accessible through 70*4882a593Smuzhiyun * the mini-PCIe connectors on the board. 71*4882a593Smuzhiyun */ 72*4882a593Smuzhiyun pcie@2,0 { 73*4882a593Smuzhiyun /* Port 1, Lane 0. CON3, nearest power. */ 74*4882a593Smuzhiyun reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>; 75*4882a593Smuzhiyun status = "okay"; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun sfp: sfp { 81*4882a593Smuzhiyun compatible = "sff,sfp"; 82*4882a593Smuzhiyun i2c-bus = <&i2c1>; 83*4882a593Smuzhiyun los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>; 84*4882a593Smuzhiyun mod-def0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>; 85*4882a593Smuzhiyun tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>; 86*4882a593Smuzhiyun tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>; 87*4882a593Smuzhiyun maximum-power-milliwatt = <2000>; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun}; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyunð1 { 92*4882a593Smuzhiyun /* ethernet@30000 */ 93*4882a593Smuzhiyun bm,pool-long = <2>; 94*4882a593Smuzhiyun bm,pool-short = <1>; 95*4882a593Smuzhiyun buffer-manager = <&bm>; 96*4882a593Smuzhiyun phys = <&comphy1 1>; 97*4882a593Smuzhiyun phy-mode = "sgmii"; 98*4882a593Smuzhiyun status = "okay"; 99*4882a593Smuzhiyun}; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyunð2 { 102*4882a593Smuzhiyun /* ethernet@34000 */ 103*4882a593Smuzhiyun bm,pool-long = <3>; 104*4882a593Smuzhiyun bm,pool-short = <1>; 105*4882a593Smuzhiyun buffer-manager = <&bm>; 106*4882a593Smuzhiyun managed = "in-band-status"; 107*4882a593Smuzhiyun phys = <&comphy5 2>; 108*4882a593Smuzhiyun phy-mode = "sgmii"; 109*4882a593Smuzhiyun sfp = <&sfp>; 110*4882a593Smuzhiyun status = "okay"; 111*4882a593Smuzhiyun}; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun&i2c0 { 114*4882a593Smuzhiyun /* 115*4882a593Smuzhiyun * PCA9655 GPIO expander, up to 1MHz clock. 116*4882a593Smuzhiyun * 0-CON3 CLKREQ# 117*4882a593Smuzhiyun * 1-CON3 PERST# 118*4882a593Smuzhiyun * 2- 119*4882a593Smuzhiyun * 3-CON3 W_DISABLE 120*4882a593Smuzhiyun * 4- 121*4882a593Smuzhiyun * 5-USB3 overcurrent 122*4882a593Smuzhiyun * 6-USB3 power 123*4882a593Smuzhiyun * 7- 124*4882a593Smuzhiyun * 8-JP4 P1 125*4882a593Smuzhiyun * 9-JP4 P4 126*4882a593Smuzhiyun * 10-JP4 P5 127*4882a593Smuzhiyun * 11-m.2 DEVSLP 128*4882a593Smuzhiyun * 12-SFP_LOS 129*4882a593Smuzhiyun * 13-SFP_TX_FAULT 130*4882a593Smuzhiyun * 14-SFP_TX_DISABLE 131*4882a593Smuzhiyun * 15-SFP_MOD_DEF0 132*4882a593Smuzhiyun */ 133*4882a593Smuzhiyun expander0: gpio-expander@20 { 134*4882a593Smuzhiyun /* 135*4882a593Smuzhiyun * This is how it should be: 136*4882a593Smuzhiyun * compatible = "onnn,pca9655", "nxp,pca9555"; 137*4882a593Smuzhiyun * but you can't do this because of the way I2C works. 138*4882a593Smuzhiyun */ 139*4882a593Smuzhiyun compatible = "nxp,pca9555"; 140*4882a593Smuzhiyun gpio-controller; 141*4882a593Smuzhiyun #gpio-cells = <2>; 142*4882a593Smuzhiyun reg = <0x20>; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun pcie1_0_clkreq { 145*4882a593Smuzhiyun gpio-hog; 146*4882a593Smuzhiyun gpios = <0 GPIO_ACTIVE_LOW>; 147*4882a593Smuzhiyun input; 148*4882a593Smuzhiyun line-name = "pcie1.0-clkreq"; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun pcie1_0_w_disable { 151*4882a593Smuzhiyun gpio-hog; 152*4882a593Smuzhiyun gpios = <3 GPIO_ACTIVE_LOW>; 153*4882a593Smuzhiyun output-low; 154*4882a593Smuzhiyun line-name = "pcie1.0-w-disable"; 155*4882a593Smuzhiyun }; 156*4882a593Smuzhiyun usb3_ilimit { 157*4882a593Smuzhiyun gpio-hog; 158*4882a593Smuzhiyun gpios = <5 GPIO_ACTIVE_LOW>; 159*4882a593Smuzhiyun input; 160*4882a593Smuzhiyun line-name = "usb3-current-limit"; 161*4882a593Smuzhiyun }; 162*4882a593Smuzhiyun usb3_power { 163*4882a593Smuzhiyun gpio-hog; 164*4882a593Smuzhiyun gpios = <6 GPIO_ACTIVE_HIGH>; 165*4882a593Smuzhiyun output-high; 166*4882a593Smuzhiyun line-name = "usb3-power"; 167*4882a593Smuzhiyun }; 168*4882a593Smuzhiyun m2_devslp { 169*4882a593Smuzhiyun gpio-hog; 170*4882a593Smuzhiyun gpios = <11 GPIO_ACTIVE_HIGH>; 171*4882a593Smuzhiyun output-low; 172*4882a593Smuzhiyun line-name = "m.2 devslp"; 173*4882a593Smuzhiyun }; 174*4882a593Smuzhiyun }; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun /* The MCP3021 supports standard and fast modes */ 177*4882a593Smuzhiyun mikrobus_adc: mcp3021@4c { 178*4882a593Smuzhiyun compatible = "microchip,mcp3021"; 179*4882a593Smuzhiyun reg = <0x4c>; 180*4882a593Smuzhiyun }; 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun eeprom@52 { 183*4882a593Smuzhiyun compatible = "atmel,24c02"; 184*4882a593Smuzhiyun reg = <0x52>; 185*4882a593Smuzhiyun pagesize = <16>; 186*4882a593Smuzhiyun }; 187*4882a593Smuzhiyun}; 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun&i2c1 { 190*4882a593Smuzhiyun /* 191*4882a593Smuzhiyun * Routed to SFP, mikrobus, and PCIe. 192*4882a593Smuzhiyun * SFP limits this to 100kHz, and requires an AT24C01A/02/04 with 193*4882a593Smuzhiyun * address pins tied low, which takes addresses 0x50 and 0x51. 194*4882a593Smuzhiyun * Mikrobus doesn't specify beyond an I2C bus being present. 195*4882a593Smuzhiyun * PCIe uses ARP to assign addresses, or 0x63-0x64. 196*4882a593Smuzhiyun */ 197*4882a593Smuzhiyun clock-frequency = <100000>; 198*4882a593Smuzhiyun pinctrl-0 = <&clearfog_i2c1_pins>; 199*4882a593Smuzhiyun pinctrl-names = "default"; 200*4882a593Smuzhiyun status = "okay"; 201*4882a593Smuzhiyun}; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun&pinctrl { 204*4882a593Smuzhiyun clearfog_i2c1_pins: i2c1-pins { 205*4882a593Smuzhiyun /* SFP, PCIe, mSATA, mikrobus */ 206*4882a593Smuzhiyun marvell,pins = "mpp26", "mpp27"; 207*4882a593Smuzhiyun marvell,function = "i2c1"; 208*4882a593Smuzhiyun }; 209*4882a593Smuzhiyun clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins { 210*4882a593Smuzhiyun marvell,pins = "mpp20"; 211*4882a593Smuzhiyun marvell,function = "gpio"; 212*4882a593Smuzhiyun }; 213*4882a593Smuzhiyun mikro_pins: mikro-pins { 214*4882a593Smuzhiyun /* int: mpp22 rst: mpp29 */ 215*4882a593Smuzhiyun marvell,pins = "mpp22", "mpp29"; 216*4882a593Smuzhiyun marvell,function = "gpio"; 217*4882a593Smuzhiyun }; 218*4882a593Smuzhiyun mikro_spi_pins: mikro-spi-pins { 219*4882a593Smuzhiyun marvell,pins = "mpp43"; 220*4882a593Smuzhiyun marvell,function = "spi1"; 221*4882a593Smuzhiyun }; 222*4882a593Smuzhiyun mikro_uart_pins: mikro-uart-pins { 223*4882a593Smuzhiyun marvell,pins = "mpp24", "mpp25"; 224*4882a593Smuzhiyun marvell,function = "ua1"; 225*4882a593Smuzhiyun }; 226*4882a593Smuzhiyun}; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun&spi1 { 229*4882a593Smuzhiyun /* 230*4882a593Smuzhiyun * Add SPI CS pins for clearfog: 231*4882a593Smuzhiyun * CS0: W25Q32 232*4882a593Smuzhiyun * CS1: PIC microcontroller (Pro models) 233*4882a593Smuzhiyun * CS2: mikrobus 234*4882a593Smuzhiyun */ 235*4882a593Smuzhiyun pinctrl-0 = <&spi1_pins &mikro_spi_pins>; 236*4882a593Smuzhiyun pinctrl-names = "default"; 237*4882a593Smuzhiyun status = "okay"; 238*4882a593Smuzhiyun}; 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun&uart1 { 241*4882a593Smuzhiyun /* mikrobus uart */ 242*4882a593Smuzhiyun pinctrl-0 = <&mikro_uart_pins>; 243*4882a593Smuzhiyun pinctrl-names = "default"; 244*4882a593Smuzhiyun status = "okay"; 245*4882a593Smuzhiyun}; 246