xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/armada-388-clearfog.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Device Tree file for SolidRun Clearfog Pro revision A1 rev 2.0 (88F6828)
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun *  Copyright (C) 2015 Russell King
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun/dts-v1/;
9*4882a593Smuzhiyun#include "armada-388-clearfog.dtsi"
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun/ {
12*4882a593Smuzhiyun	model = "SolidRun Clearfog A1";
13*4882a593Smuzhiyun	compatible = "solidrun,clearfog-a1", "marvell,armada388",
14*4882a593Smuzhiyun		"marvell,armada385", "marvell,armada380";
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun	soc {
17*4882a593Smuzhiyun		internal-regs {
18*4882a593Smuzhiyun			usb3@f0000 {
19*4882a593Smuzhiyun				/* CON2, nearest CPU, USB2 only. */
20*4882a593Smuzhiyun				status = "okay";
21*4882a593Smuzhiyun			};
22*4882a593Smuzhiyun		};
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun		pcie {
25*4882a593Smuzhiyun			pcie@3,0 {
26*4882a593Smuzhiyun				/* Port 2, Lane 0. CON2, nearest CPU. */
27*4882a593Smuzhiyun				reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
28*4882a593Smuzhiyun				status = "okay";
29*4882a593Smuzhiyun			};
30*4882a593Smuzhiyun		};
31*4882a593Smuzhiyun	};
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun	gpio-keys {
34*4882a593Smuzhiyun		compatible = "gpio-keys";
35*4882a593Smuzhiyun		pinctrl-0 = <&rear_button_pins>;
36*4882a593Smuzhiyun		pinctrl-names = "default";
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun		button_0 {
39*4882a593Smuzhiyun			/* The rear SW3 button */
40*4882a593Smuzhiyun			label = "Rear Button";
41*4882a593Smuzhiyun			gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
42*4882a593Smuzhiyun			linux,can-disable;
43*4882a593Smuzhiyun			linux,code = <BTN_0>;
44*4882a593Smuzhiyun		};
45*4882a593Smuzhiyun	};
46*4882a593Smuzhiyun};
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun&eth1 {
49*4882a593Smuzhiyun	/* ethernet@30000 */
50*4882a593Smuzhiyun	fixed-link {
51*4882a593Smuzhiyun		speed = <1000>;
52*4882a593Smuzhiyun		full-duplex;
53*4882a593Smuzhiyun	};
54*4882a593Smuzhiyun};
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun&expander0 {
57*4882a593Smuzhiyun	/*
58*4882a593Smuzhiyun	 * PCA9655 GPIO expander:
59*4882a593Smuzhiyun	 *  0-CON3 CLKREQ#
60*4882a593Smuzhiyun	 *  1-CON3 PERST#
61*4882a593Smuzhiyun	 *  2-CON2 PERST#
62*4882a593Smuzhiyun	 *  3-CON3 W_DISABLE
63*4882a593Smuzhiyun	 *  4-CON2 CLKREQ#
64*4882a593Smuzhiyun	 *  5-USB3 overcurrent
65*4882a593Smuzhiyun	 *  6-USB3 power
66*4882a593Smuzhiyun	 *  7-CON2 W_DISABLE
67*4882a593Smuzhiyun	 *  8-JP4 P1
68*4882a593Smuzhiyun	 *  9-JP4 P4
69*4882a593Smuzhiyun	 * 10-JP4 P5
70*4882a593Smuzhiyun	 * 11-m.2 DEVSLP
71*4882a593Smuzhiyun	 * 12-SFP_LOS
72*4882a593Smuzhiyun	 * 13-SFP_TX_FAULT
73*4882a593Smuzhiyun	 * 14-SFP_TX_DISABLE
74*4882a593Smuzhiyun	 * 15-SFP_MOD_DEF0
75*4882a593Smuzhiyun	 */
76*4882a593Smuzhiyun	pcie2_0_clkreq {
77*4882a593Smuzhiyun		gpio-hog;
78*4882a593Smuzhiyun		gpios = <4 GPIO_ACTIVE_LOW>;
79*4882a593Smuzhiyun		input;
80*4882a593Smuzhiyun		line-name = "pcie2.0-clkreq";
81*4882a593Smuzhiyun	};
82*4882a593Smuzhiyun	pcie2_0_w_disable {
83*4882a593Smuzhiyun		gpio-hog;
84*4882a593Smuzhiyun		gpios = <7 GPIO_ACTIVE_LOW>;
85*4882a593Smuzhiyun		output-low;
86*4882a593Smuzhiyun		line-name = "pcie2.0-w-disable";
87*4882a593Smuzhiyun	};
88*4882a593Smuzhiyun};
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun&mdio {
91*4882a593Smuzhiyun	status = "okay";
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun	switch@4 {
94*4882a593Smuzhiyun		compatible = "marvell,mv88e6085";
95*4882a593Smuzhiyun		#address-cells = <1>;
96*4882a593Smuzhiyun		#size-cells = <0>;
97*4882a593Smuzhiyun		reg = <4>;
98*4882a593Smuzhiyun		pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
99*4882a593Smuzhiyun		pinctrl-names = "default";
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun		ports {
102*4882a593Smuzhiyun			#address-cells = <1>;
103*4882a593Smuzhiyun			#size-cells = <0>;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun			port@0 {
106*4882a593Smuzhiyun				reg = <0>;
107*4882a593Smuzhiyun				label = "lan5";
108*4882a593Smuzhiyun			};
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun			port@1 {
111*4882a593Smuzhiyun				reg = <1>;
112*4882a593Smuzhiyun				label = "lan4";
113*4882a593Smuzhiyun			};
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun			port@2 {
116*4882a593Smuzhiyun				reg = <2>;
117*4882a593Smuzhiyun				label = "lan3";
118*4882a593Smuzhiyun			};
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun			port@3 {
121*4882a593Smuzhiyun				reg = <3>;
122*4882a593Smuzhiyun				label = "lan2";
123*4882a593Smuzhiyun			};
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun			port@4 {
126*4882a593Smuzhiyun				reg = <4>;
127*4882a593Smuzhiyun				label = "lan1";
128*4882a593Smuzhiyun			};
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun			port@5 {
131*4882a593Smuzhiyun				reg = <5>;
132*4882a593Smuzhiyun				label = "cpu";
133*4882a593Smuzhiyun				ethernet = <&eth1>;
134*4882a593Smuzhiyun				fixed-link {
135*4882a593Smuzhiyun					speed = <1000>;
136*4882a593Smuzhiyun					full-duplex;
137*4882a593Smuzhiyun				};
138*4882a593Smuzhiyun			};
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun			port@6 {
141*4882a593Smuzhiyun				/* 88E1512 external phy */
142*4882a593Smuzhiyun				reg = <6>;
143*4882a593Smuzhiyun				label = "lan6";
144*4882a593Smuzhiyun				fixed-link {
145*4882a593Smuzhiyun					speed = <1000>;
146*4882a593Smuzhiyun					full-duplex;
147*4882a593Smuzhiyun				};
148*4882a593Smuzhiyun			};
149*4882a593Smuzhiyun		};
150*4882a593Smuzhiyun	};
151*4882a593Smuzhiyun};
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun&pinctrl {
154*4882a593Smuzhiyun	clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
155*4882a593Smuzhiyun		marvell,pins = "mpp46";
156*4882a593Smuzhiyun		marvell,function = "ref";
157*4882a593Smuzhiyun	};
158*4882a593Smuzhiyun	clearfog_dsa0_pins: clearfog-dsa0-pins {
159*4882a593Smuzhiyun		marvell,pins = "mpp23", "mpp41";
160*4882a593Smuzhiyun		marvell,function = "gpio";
161*4882a593Smuzhiyun	};
162*4882a593Smuzhiyun	clearfog_spi1_cs_pins: spi1-cs-pins {
163*4882a593Smuzhiyun		marvell,pins = "mpp55";
164*4882a593Smuzhiyun		marvell,function = "spi1";
165*4882a593Smuzhiyun	};
166*4882a593Smuzhiyun	rear_button_pins: rear-button-pins {
167*4882a593Smuzhiyun		marvell,pins = "mpp34";
168*4882a593Smuzhiyun		marvell,function = "gpio";
169*4882a593Smuzhiyun	};
170*4882a593Smuzhiyun};
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun&spi1 {
173*4882a593Smuzhiyun	/*
174*4882a593Smuzhiyun	 * Add SPI CS pins for clearfog:
175*4882a593Smuzhiyun	 * CS0: W25Q32
176*4882a593Smuzhiyun	 * CS1:
177*4882a593Smuzhiyun	 * CS2: mikrobus
178*4882a593Smuzhiyun	 */
179*4882a593Smuzhiyun	pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>;
180*4882a593Smuzhiyun};
181