1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree common file for the Seagate Personal Cloud NAS 1 and 2-Bay 4*4882a593Smuzhiyun * (Armada 370 SoC). 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2015 Seagate 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Author: Simon Guinot <simon.guinot@sequanux.org> 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/* 12*4882a593Smuzhiyun * TODO: add support for the white SATA LED. 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun#include "armada-370.dtsi" 16*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 17*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun/ { 20*4882a593Smuzhiyun chosen { 21*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun memory@0 { 25*4882a593Smuzhiyun device_type = "memory"; 26*4882a593Smuzhiyun reg = <0x00000000 0x20000000>; /* 512 MB */ 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun soc { 30*4882a593Smuzhiyun ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 31*4882a593Smuzhiyun MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun internal-regs { 34*4882a593Smuzhiyun coherency-fabric@20200 { 35*4882a593Smuzhiyun broken-idle; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun serial@12000 { 39*4882a593Smuzhiyun status = "okay"; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun ethernet@74000 { 43*4882a593Smuzhiyun status = "okay"; 44*4882a593Smuzhiyun pinctrl-0 = <&ge1_rgmii_pins>; 45*4882a593Smuzhiyun pinctrl-names = "default"; 46*4882a593Smuzhiyun phy = <&phy0>; 47*4882a593Smuzhiyun phy-mode = "rgmii-id"; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun usb@50000 { 51*4882a593Smuzhiyun status = "okay"; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun regulators { 57*4882a593Smuzhiyun compatible = "simple-bus"; 58*4882a593Smuzhiyun #address-cells = <1>; 59*4882a593Smuzhiyun #size-cells = <0>; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun regulator@0 { 62*4882a593Smuzhiyun compatible = "regulator-fixed"; 63*4882a593Smuzhiyun reg = <0>; 64*4882a593Smuzhiyun regulator-name = "USB Power"; 65*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 66*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 67*4882a593Smuzhiyun regulator-always-on; 68*4882a593Smuzhiyun regulator-boot-on; 69*4882a593Smuzhiyun gpio = <&gpio1 27 GPIO_ACTIVE_LOW>; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun regulator@1 { 72*4882a593Smuzhiyun compatible = "regulator-fixed"; 73*4882a593Smuzhiyun reg = <1>; 74*4882a593Smuzhiyun regulator-name = "SATA0 power"; 75*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 76*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 77*4882a593Smuzhiyun enable-active-high; 78*4882a593Smuzhiyun regulator-always-on; 79*4882a593Smuzhiyun regulator-boot-on; 80*4882a593Smuzhiyun gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun gpio-keys { 85*4882a593Smuzhiyun compatible = "gpio-keys"; 86*4882a593Smuzhiyun #address-cells = <1>; 87*4882a593Smuzhiyun #size-cells = <0>; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun power { 90*4882a593Smuzhiyun label = "Power button"; 91*4882a593Smuzhiyun linux,code = <KEY_POWER>; 92*4882a593Smuzhiyun gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; 93*4882a593Smuzhiyun debounce-interval = <100>; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun reset { 96*4882a593Smuzhiyun label = "Reset Button"; 97*4882a593Smuzhiyun linux,code = <KEY_RESTART>; 98*4882a593Smuzhiyun gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; 99*4882a593Smuzhiyun debounce-interval = <100>; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun button { 102*4882a593Smuzhiyun label = "USB VBUS error"; 103*4882a593Smuzhiyun linux,code = <KEY_UNKNOWN>; 104*4882a593Smuzhiyun gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; 105*4882a593Smuzhiyun debounce-interval = <100>; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun gpio-leds { 110*4882a593Smuzhiyun compatible = "gpio-leds"; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun red-sata0 { 113*4882a593Smuzhiyun label = "cumulus:red:sata0"; 114*4882a593Smuzhiyun gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 115*4882a593Smuzhiyun default-state = "off"; 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun gpio_poweroff { 120*4882a593Smuzhiyun compatible = "gpio-poweroff"; 121*4882a593Smuzhiyun gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun}; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun&pciec { 126*4882a593Smuzhiyun status = "okay"; 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun /* USB 3.0 Bridge ASM1042A */ 129*4882a593Smuzhiyun pcie@1,0 { 130*4882a593Smuzhiyun status = "okay"; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun}; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun&mdio { 135*4882a593Smuzhiyun pinctrl-0 = <&mdio_pins>; 136*4882a593Smuzhiyun pinctrl-names = "default"; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun phy0: ethernet-phy@0 { 139*4882a593Smuzhiyun reg = <0>; 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun}; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun&pinctrl { 144*4882a593Smuzhiyun pinctrl-0 = <&sata_led_pin>; 145*4882a593Smuzhiyun pinctrl-names = "default"; 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun sata_led_pin: sata-led-pin { 148*4882a593Smuzhiyun marvell,pins = "mpp60"; 149*4882a593Smuzhiyun marvell,function = "sata0"; 150*4882a593Smuzhiyun }; 151*4882a593Smuzhiyun gpio_led_pin: gpio-led-pin { 152*4882a593Smuzhiyun marvell,pins = "mpp60"; 153*4882a593Smuzhiyun marvell,function = "gpio"; 154*4882a593Smuzhiyun }; 155*4882a593Smuzhiyun}; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun&spi0 { 158*4882a593Smuzhiyun status = "okay"; 159*4882a593Smuzhiyun pinctrl-0 = <&spi0_pins2>; 160*4882a593Smuzhiyun pinctrl-names = "default"; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun spi-flash@0 { 163*4882a593Smuzhiyun #address-cells = <1>; 164*4882a593Smuzhiyun #size-cells = <1>; 165*4882a593Smuzhiyun /* MX25L8006E */ 166*4882a593Smuzhiyun compatible = "mxicy,mx25l8005", "jedec,spi-nor"; 167*4882a593Smuzhiyun reg = <0>; /* Chip select 0 */ 168*4882a593Smuzhiyun spi-max-frequency = <50000000>; 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun partition@0 { 171*4882a593Smuzhiyun label = "u-boot"; 172*4882a593Smuzhiyun reg = <0x0 0x100000>; 173*4882a593Smuzhiyun }; 174*4882a593Smuzhiyun }; 175*4882a593Smuzhiyun}; 176