xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/armada-370-netgear-rn102.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Device Tree file for NETGEAR ReadyNAS 102
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun/dts-v1/;
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
11*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
12*4882a593Smuzhiyun#include "armada-370.dtsi"
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun/ {
15*4882a593Smuzhiyun	model = "NETGEAR ReadyNAS 102";
16*4882a593Smuzhiyun	compatible = "netgear,readynas-102", "marvell,armada370", "marvell,armada-370-xp";
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun	chosen {
19*4882a593Smuzhiyun		stdout-path = "serial0:115200n8";
20*4882a593Smuzhiyun	};
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun	memory@0 {
23*4882a593Smuzhiyun		device_type = "memory";
24*4882a593Smuzhiyun		reg = <0x00000000 0x20000000>; /* 512 MB */
25*4882a593Smuzhiyun	};
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun	soc {
28*4882a593Smuzhiyun		ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
29*4882a593Smuzhiyun			  MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000
30*4882a593Smuzhiyun			  MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun		internal-regs {
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun			/* RTC is provided by Intersil ISL12057 I2C RTC chip */
35*4882a593Smuzhiyun			rtc@10300 {
36*4882a593Smuzhiyun				status = "disabled";
37*4882a593Smuzhiyun			};
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun			serial@12000 {
40*4882a593Smuzhiyun				status = "okay";
41*4882a593Smuzhiyun			};
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun			/* eSATA interface */
44*4882a593Smuzhiyun			sata@a0000 {
45*4882a593Smuzhiyun				nr-ports = <1>;
46*4882a593Smuzhiyun				status = "okay";
47*4882a593Smuzhiyun			};
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun			ethernet@74000 {
50*4882a593Smuzhiyun				pinctrl-0 = <&ge1_rgmii_pins>;
51*4882a593Smuzhiyun				pinctrl-names = "default";
52*4882a593Smuzhiyun				status = "okay";
53*4882a593Smuzhiyun				phy = <&phy0>;
54*4882a593Smuzhiyun				phy-mode = "rgmii-id";
55*4882a593Smuzhiyun			};
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun			usb@50000 {
58*4882a593Smuzhiyun				status = "okay";
59*4882a593Smuzhiyun			};
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun			i2c@11000 {
62*4882a593Smuzhiyun				clock-frequency = <100000>;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun				pinctrl-0 = <&i2c0_pins>;
65*4882a593Smuzhiyun				pinctrl-names = "default";
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun				status = "okay";
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun				isl12057: rtc@68 {
70*4882a593Smuzhiyun					compatible = "isil,isl12057";
71*4882a593Smuzhiyun					reg = <0x68>;
72*4882a593Smuzhiyun					wakeup-source;
73*4882a593Smuzhiyun				};
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun				g762: g762@3e {
76*4882a593Smuzhiyun					compatible = "gmt,g762";
77*4882a593Smuzhiyun					reg = <0x3e>;
78*4882a593Smuzhiyun					clocks = <&g762_clk>; /* input clock */
79*4882a593Smuzhiyun					fan_gear_mode = <0>;
80*4882a593Smuzhiyun					fan_startv = <1>;
81*4882a593Smuzhiyun					pwm_polarity = <0>;
82*4882a593Smuzhiyun				};
83*4882a593Smuzhiyun			};
84*4882a593Smuzhiyun		};
85*4882a593Smuzhiyun	};
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun	clocks {
88*4882a593Smuzhiyun	       g762_clk: g762-oscillator {
89*4882a593Smuzhiyun			 compatible = "fixed-clock";
90*4882a593Smuzhiyun			 #clock-cells = <0>;
91*4882a593Smuzhiyun			 clock-frequency = <8192>;
92*4882a593Smuzhiyun	       };
93*4882a593Smuzhiyun	};
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun	gpio-leds {
96*4882a593Smuzhiyun		compatible = "gpio-leds";
97*4882a593Smuzhiyun		pinctrl-0 = <&power_led_pin
98*4882a593Smuzhiyun			     &sata1_led_pin
99*4882a593Smuzhiyun			     &sata2_led_pin
100*4882a593Smuzhiyun			     &backup_led_pin>;
101*4882a593Smuzhiyun		pinctrl-names = "default";
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun		blue-power-led {
104*4882a593Smuzhiyun			label = "rn102:blue:pwr";
105*4882a593Smuzhiyun			gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
106*4882a593Smuzhiyun			default-state = "keep";
107*4882a593Smuzhiyun		};
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun		blue-sata1-led {
110*4882a593Smuzhiyun			label = "rn102:blue:sata1";
111*4882a593Smuzhiyun			gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
112*4882a593Smuzhiyun			default-state = "on";
113*4882a593Smuzhiyun		};
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun		blue-sata2-led {
116*4882a593Smuzhiyun			label = "rn102:blue:sata2";
117*4882a593Smuzhiyun			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
118*4882a593Smuzhiyun			default-state = "on";
119*4882a593Smuzhiyun		};
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun		blue-backup-led {
122*4882a593Smuzhiyun			label = "rn102:blue:backup";
123*4882a593Smuzhiyun			gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
124*4882a593Smuzhiyun			default-state = "on";
125*4882a593Smuzhiyun		};
126*4882a593Smuzhiyun	};
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun	gpio-keys {
129*4882a593Smuzhiyun		compatible = "gpio-keys";
130*4882a593Smuzhiyun		pinctrl-0 = <&power_button_pin
131*4882a593Smuzhiyun			     &reset_button_pin
132*4882a593Smuzhiyun			     &backup_button_pin>;
133*4882a593Smuzhiyun		pinctrl-names = "default";
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun		power-button {
136*4882a593Smuzhiyun			label = "Power Button";
137*4882a593Smuzhiyun			linux,code = <KEY_POWER>;
138*4882a593Smuzhiyun			gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
139*4882a593Smuzhiyun		};
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun		reset-button {
142*4882a593Smuzhiyun			label = "Reset Button";
143*4882a593Smuzhiyun			linux,code = <KEY_RESTART>;
144*4882a593Smuzhiyun			gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
145*4882a593Smuzhiyun		};
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun		backup-button {
148*4882a593Smuzhiyun			label = "Backup Button";
149*4882a593Smuzhiyun			linux,code = <KEY_COPY>;
150*4882a593Smuzhiyun			gpios = <&gpio1 26 GPIO_ACTIVE_LOW>;
151*4882a593Smuzhiyun		};
152*4882a593Smuzhiyun	};
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun	gpio-poweroff {
155*4882a593Smuzhiyun		compatible = "gpio-poweroff";
156*4882a593Smuzhiyun		pinctrl-0 = <&poweroff>;
157*4882a593Smuzhiyun		pinctrl-names = "default";
158*4882a593Smuzhiyun		gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
159*4882a593Smuzhiyun	};
160*4882a593Smuzhiyun};
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun&pciec {
163*4882a593Smuzhiyun	status = "okay";
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun	/* Connected to Marvell 88SE9170 SATA controller */
166*4882a593Smuzhiyun	pcie@1,0 {
167*4882a593Smuzhiyun		/* Port 0, Lane 0 */
168*4882a593Smuzhiyun		status = "okay";
169*4882a593Smuzhiyun	};
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun	/* Connected to FL1009 USB 3.0 controller */
172*4882a593Smuzhiyun	pcie@2,0 {
173*4882a593Smuzhiyun		/* Port 1, Lane 0 */
174*4882a593Smuzhiyun		status = "okay";
175*4882a593Smuzhiyun	};
176*4882a593Smuzhiyun};
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun&mdio {
179*4882a593Smuzhiyun	pinctrl-0 = <&mdio_pins>;
180*4882a593Smuzhiyun	pinctrl-names = "default";
181*4882a593Smuzhiyun	phy0: ethernet-phy@0 { /* Marvell 88E1318 */
182*4882a593Smuzhiyun		reg = <0>;
183*4882a593Smuzhiyun	};
184*4882a593Smuzhiyun};
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun&pinctrl {
187*4882a593Smuzhiyun	power_led_pin: power-led-pin {
188*4882a593Smuzhiyun		marvell,pins = "mpp57";
189*4882a593Smuzhiyun		marvell,function = "gpio";
190*4882a593Smuzhiyun	};
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun	sata1_led_pin: sata1-led-pin {
193*4882a593Smuzhiyun		marvell,pins = "mpp15";
194*4882a593Smuzhiyun		marvell,function = "gpio";
195*4882a593Smuzhiyun	};
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun	sata2_led_pin: sata2-led-pin {
198*4882a593Smuzhiyun		marvell,pins = "mpp14";
199*4882a593Smuzhiyun		marvell,function = "gpio";
200*4882a593Smuzhiyun	};
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun	backup_led_pin: backup-led-pin {
203*4882a593Smuzhiyun		marvell,pins = "mpp56";
204*4882a593Smuzhiyun		marvell,function = "gpio";
205*4882a593Smuzhiyun	};
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun	backup_button_pin: backup-button-pin {
208*4882a593Smuzhiyun		marvell,pins = "mpp58";
209*4882a593Smuzhiyun		marvell,function = "gpio";
210*4882a593Smuzhiyun	};
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun	power_button_pin: power-button-pin {
213*4882a593Smuzhiyun		marvell,pins = "mpp62";
214*4882a593Smuzhiyun		marvell,function = "gpio";
215*4882a593Smuzhiyun	};
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun	reset_button_pin: reset-button-pin {
218*4882a593Smuzhiyun		marvell,pins = "mpp6";
219*4882a593Smuzhiyun		marvell,function = "gpio";
220*4882a593Smuzhiyun	};
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun	poweroff: poweroff {
223*4882a593Smuzhiyun		marvell,pins = "mpp8";
224*4882a593Smuzhiyun		marvell,function = "gpio";
225*4882a593Smuzhiyun	};
226*4882a593Smuzhiyun};
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun&nand_controller {
229*4882a593Smuzhiyun	status = "okay";
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun	nand@0 {
232*4882a593Smuzhiyun		reg = <0>;
233*4882a593Smuzhiyun		label = "pxa3xx_nand-0";
234*4882a593Smuzhiyun		nand-rb = <0>;
235*4882a593Smuzhiyun		marvell,nand-keep-config;
236*4882a593Smuzhiyun		nand-on-flash-bbt;
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun		/* Use Hardware BCH ECC */
239*4882a593Smuzhiyun		nand-ecc-strength = <4>;
240*4882a593Smuzhiyun		nand-ecc-step-size = <512>;
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun		partitions {
243*4882a593Smuzhiyun			compatible = "fixed-partitions";
244*4882a593Smuzhiyun			#address-cells = <1>;
245*4882a593Smuzhiyun			#size-cells = <1>;
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun			partition@0 {
248*4882a593Smuzhiyun				label = "u-boot";
249*4882a593Smuzhiyun				reg = <0x0000000 0x180000>;  /* 1.5MB */
250*4882a593Smuzhiyun				read-only;
251*4882a593Smuzhiyun			};
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun			partition@180000 {
254*4882a593Smuzhiyun				label = "u-boot-env";
255*4882a593Smuzhiyun				reg = <0x180000 0x20000>;    /* 128KB */
256*4882a593Smuzhiyun				read-only;
257*4882a593Smuzhiyun			};
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun			partition@200000 {
260*4882a593Smuzhiyun				label = "uImage";
261*4882a593Smuzhiyun				reg = <0x0200000 0x600000>;    /* 6MB */
262*4882a593Smuzhiyun			};
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun			partition@800000 {
265*4882a593Smuzhiyun				label = "minirootfs";
266*4882a593Smuzhiyun				reg = <0x0800000 0x400000>;    /* 4MB */
267*4882a593Smuzhiyun			};
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun			/* Last MB is for the BBT, i.e. not writable */
270*4882a593Smuzhiyun			partition@c00000 {
271*4882a593Smuzhiyun				label = "ubifs";
272*4882a593Smuzhiyun				reg = <0x0c00000 0x7400000>; /* 116MB */
273*4882a593Smuzhiyun			};
274*4882a593Smuzhiyun		};
275*4882a593Smuzhiyun	};
276*4882a593Smuzhiyun};
277