1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree file for Globalscale Mirabox 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Gregory CLEMENT <gregory.clement@free-electrons.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/dts-v1/; 9*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 10*4882a593Smuzhiyun#include "armada-370.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun model = "Globalscale Mirabox"; 14*4882a593Smuzhiyun compatible = "globalscale,mirabox", "marvell,armada370", "marvell,armada-370-xp"; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun chosen { 17*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun memory@0 { 21*4882a593Smuzhiyun device_type = "memory"; 22*4882a593Smuzhiyun reg = <0x00000000 0x20000000>; /* 512 MB */ 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun soc { 26*4882a593Smuzhiyun ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000 27*4882a593Smuzhiyun MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000 28*4882a593Smuzhiyun MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun internal-regs { 31*4882a593Smuzhiyun serial@12000 { 32*4882a593Smuzhiyun status = "okay"; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun timer@20300 { 35*4882a593Smuzhiyun clock-frequency = <600000000>; 36*4882a593Smuzhiyun status = "okay"; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun gpio_leds { 40*4882a593Smuzhiyun compatible = "gpio-leds"; 41*4882a593Smuzhiyun pinctrl-names = "default"; 42*4882a593Smuzhiyun pinctrl-0 = <&pwr_led_pin &stat_led_pins>; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun green_pwr_led { 45*4882a593Smuzhiyun label = "mirabox:green:pwr"; 46*4882a593Smuzhiyun gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; 47*4882a593Smuzhiyun default-state = "keep"; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun blue_stat_led { 51*4882a593Smuzhiyun label = "mirabox:blue:stat"; 52*4882a593Smuzhiyun gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 53*4882a593Smuzhiyun default-state = "off"; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun green_stat_led { 57*4882a593Smuzhiyun label = "mirabox:green:stat"; 58*4882a593Smuzhiyun gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; 59*4882a593Smuzhiyun default-state = "off"; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun ethernet@70000 { 64*4882a593Smuzhiyun pinctrl-0 = <&ge0_rgmii_pins>; 65*4882a593Smuzhiyun pinctrl-names = "default"; 66*4882a593Smuzhiyun status = "okay"; 67*4882a593Smuzhiyun phy = <&phy0>; 68*4882a593Smuzhiyun phy-mode = "rgmii-id"; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun ethernet@74000 { 71*4882a593Smuzhiyun pinctrl-0 = <&ge1_rgmii_pins>; 72*4882a593Smuzhiyun pinctrl-names = "default"; 73*4882a593Smuzhiyun status = "okay"; 74*4882a593Smuzhiyun phy = <&phy1>; 75*4882a593Smuzhiyun phy-mode = "rgmii-id"; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun crypto@90000 { 79*4882a593Smuzhiyun status = "okay"; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun mvsdio@d4000 { 83*4882a593Smuzhiyun pinctrl-0 = <&sdio_pins3>; 84*4882a593Smuzhiyun pinctrl-names = "default"; 85*4882a593Smuzhiyun status = "okay"; 86*4882a593Smuzhiyun /* 87*4882a593Smuzhiyun * No CD or WP GPIOs: SDIO interface used for 88*4882a593Smuzhiyun * Wifi/Bluetooth chip 89*4882a593Smuzhiyun */ 90*4882a593Smuzhiyun broken-cd; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun usb@50000 { 94*4882a593Smuzhiyun status = "okay"; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun usb@51000 { 98*4882a593Smuzhiyun status = "okay"; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun i2c@11000 { 102*4882a593Smuzhiyun status = "okay"; 103*4882a593Smuzhiyun clock-frequency = <100000>; 104*4882a593Smuzhiyun pca9505: pca9505@25 { 105*4882a593Smuzhiyun compatible = "nxp,pca9505"; 106*4882a593Smuzhiyun gpio-controller; 107*4882a593Smuzhiyun #gpio-cells = <2>; 108*4882a593Smuzhiyun reg = <0x25>; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun}; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun&pciec { 116*4882a593Smuzhiyun status = "okay"; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun /* Internal mini-PCIe connector */ 119*4882a593Smuzhiyun pcie@1,0 { 120*4882a593Smuzhiyun /* Port 0, Lane 0 */ 121*4882a593Smuzhiyun status = "okay"; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /* Connected on the PCB to a USB 3.0 XHCI controller */ 125*4882a593Smuzhiyun pcie@2,0 { 126*4882a593Smuzhiyun /* Port 1, Lane 0 */ 127*4882a593Smuzhiyun status = "okay"; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun}; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun&mdio { 132*4882a593Smuzhiyun pinctrl-0 = <&mdio_pins>; 133*4882a593Smuzhiyun pinctrl-names = "default"; 134*4882a593Smuzhiyun phy0: ethernet-phy@0 { 135*4882a593Smuzhiyun reg = <0>; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun phy1: ethernet-phy@1 { 139*4882a593Smuzhiyun reg = <1>; 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun}; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun&pinctrl { 144*4882a593Smuzhiyun pwr_led_pin: pwr-led-pin { 145*4882a593Smuzhiyun marvell,pins = "mpp63"; 146*4882a593Smuzhiyun marvell,function = "gpio"; 147*4882a593Smuzhiyun }; 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun stat_led_pins: stat-led-pins { 150*4882a593Smuzhiyun marvell,pins = "mpp64", "mpp65"; 151*4882a593Smuzhiyun marvell,function = "gpio"; 152*4882a593Smuzhiyun }; 153*4882a593Smuzhiyun}; 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun&nand_controller { 156*4882a593Smuzhiyun status = "okay"; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun nand@0 { 159*4882a593Smuzhiyun reg = <0>; 160*4882a593Smuzhiyun label = "pxa3xx_nand-0"; 161*4882a593Smuzhiyun nand-rb = <0>; 162*4882a593Smuzhiyun marvell,nand-keep-config; 163*4882a593Smuzhiyun nand-on-flash-bbt; 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun partitions { 166*4882a593Smuzhiyun compatible = "fixed-partitions"; 167*4882a593Smuzhiyun #address-cells = <1>; 168*4882a593Smuzhiyun #size-cells = <1>; 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun partition@0 { 171*4882a593Smuzhiyun label = "U-Boot"; 172*4882a593Smuzhiyun reg = <0 0x400000>; 173*4882a593Smuzhiyun }; 174*4882a593Smuzhiyun partition@400000 { 175*4882a593Smuzhiyun label = "Linux"; 176*4882a593Smuzhiyun reg = <0x400000 0x400000>; 177*4882a593Smuzhiyun }; 178*4882a593Smuzhiyun partition@800000 { 179*4882a593Smuzhiyun label = "Filesystem"; 180*4882a593Smuzhiyun reg = <0x800000 0x3f800000>; 181*4882a593Smuzhiyun }; 182*4882a593Smuzhiyun }; 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun}; 185