xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/am57xx-sbc-am57x.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Support for CompuLab SBC-AM57x single board computer
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2015 CompuLab Ltd. - http://www.compulab.co.il/
6*4882a593Smuzhiyun * Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun#include "am57xx-cl-som-am57x.dts"
10*4882a593Smuzhiyun#include "compulab-sb-som.dtsi"
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun/ {
13*4882a593Smuzhiyun	model = "CompuLab CL-SOM-AM57x on SB-SOM-AM57x";
14*4882a593Smuzhiyun	compatible = "compulab,sbc-am57x", "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun	aliases {
17*4882a593Smuzhiyun		display0 = &lcd0;
18*4882a593Smuzhiyun		display1 = &hdmi;
19*4882a593Smuzhiyun	};
20*4882a593Smuzhiyun};
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun&dra7_pmx_core {
23*4882a593Smuzhiyun	uart3_pins_default: uart3_pins_default {
24*4882a593Smuzhiyun		pinctrl-single,pins = <
25*4882a593Smuzhiyun			DRA7XX_CORE_IOPAD(0x3648, PIN_INPUT_SLEW | MUX_MODE0)	/* uart3_rxd */
26*4882a593Smuzhiyun			DRA7XX_CORE_IOPAD(0x364c, PIN_INPUT_SLEW | MUX_MODE0)	/* uart3_txd */
27*4882a593Smuzhiyun		>;
28*4882a593Smuzhiyun	};
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun	mmc1_pins_default: mmc1_pins_default {
31*4882a593Smuzhiyun		pinctrl-single,pins = <
32*4882a593Smuzhiyun			DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
33*4882a593Smuzhiyun			DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc1_cmd.cmd */
34*4882a593Smuzhiyun			DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
35*4882a593Smuzhiyun			DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
36*4882a593Smuzhiyun			DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
37*4882a593Smuzhiyun			DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
38*4882a593Smuzhiyun			DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14)	/* mmc1_sdcd.gpio6_27 */
39*4882a593Smuzhiyun			DRA7XX_CORE_IOPAD(0x377c, PIN_INPUT | MUX_MODE14)	/* mmc1_sdwp.gpio6_28 */
40*4882a593Smuzhiyun		>;
41*4882a593Smuzhiyun	};
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun	usb1_pins: pinmux_usb1_pins {
44*4882a593Smuzhiyun		pinctrl-single,pins = <
45*4882a593Smuzhiyun			DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
46*4882a593Smuzhiyun		>;
47*4882a593Smuzhiyun	};
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun	i2c5_pins_default: i2c5_pins_default {
50*4882a593Smuzhiyun		pinctrl-single,pins = <
51*4882a593Smuzhiyun			DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT| MUX_MODE10)	/* mcasp1_axr0.i2c5_sda */
52*4882a593Smuzhiyun			DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT| MUX_MODE10)	/* mcasp1_axr1.i2c5_scl */
53*4882a593Smuzhiyun		>;
54*4882a593Smuzhiyun	};
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun	lcd_pins_default: lcd_pins_default {
57*4882a593Smuzhiyun		pinctrl-single,pins = <
58*4882a593Smuzhiyun			DRA7XX_CORE_IOPAD(0x3564, PIN_OUTPUT | MUX_MODE14)      /* vin2a_vsync0.gpio4_0 */
59*4882a593Smuzhiyun		>;
60*4882a593Smuzhiyun	};
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun	hdmi_pins: pinmux_hdmi_pins {
63*4882a593Smuzhiyun		pinctrl-single,pins = <
64*4882a593Smuzhiyun			DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1)	/* i2c2_sda.hdmi1_ddc_scl */
65*4882a593Smuzhiyun			DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1)	/* i2c2_scl.hdmi1_ddc_sda */
66*4882a593Smuzhiyun		>;
67*4882a593Smuzhiyun	};
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun	hdmi_conn_pins: pinmux_hdmi_conn_pins {
70*4882a593Smuzhiyun		pinctrl-single,pins = <
71*4882a593Smuzhiyun			DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT | MUX_MODE14)	/* spi1_cs2.gpio7_12 */
72*4882a593Smuzhiyun		>;
73*4882a593Smuzhiyun	};
74*4882a593Smuzhiyun};
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun&uart3 {
77*4882a593Smuzhiyun	status = "okay";
78*4882a593Smuzhiyun	interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
79*4882a593Smuzhiyun			      <&dra7_pmx_core 0x3f8>;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun	pinctrl-names = "default";
82*4882a593Smuzhiyun	pinctrl-0 = <&uart3_pins_default>;
83*4882a593Smuzhiyun};
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun&mmc1 {
86*4882a593Smuzhiyun	status = "okay";
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun	pinctrl-names = "default";
89*4882a593Smuzhiyun	pinctrl-0 = <&mmc1_pins_default>;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun	vmmc-supply = <&ldo1_reg>;
92*4882a593Smuzhiyun	bus-width = <4>;
93*4882a593Smuzhiyun	cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
94*4882a593Smuzhiyun	wp-gpios = <&gpio6 28 GPIO_ACTIVE_HIGH>;
95*4882a593Smuzhiyun};
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun&usb1 {
98*4882a593Smuzhiyun	pinctrl-names = "default";
99*4882a593Smuzhiyun	pinctrl-0 = <&usb1_pins>;
100*4882a593Smuzhiyun};
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun&i2c5 {
103*4882a593Smuzhiyun	status = "okay";
104*4882a593Smuzhiyun	pinctrl-names = "default";
105*4882a593Smuzhiyun	pinctrl-0 = <&i2c5_pins_default>;
106*4882a593Smuzhiyun	clock-frequency = <400000>;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun	eeprom_base: atmel@54 {
109*4882a593Smuzhiyun		compatible = "atmel,24c08";
110*4882a593Smuzhiyun		reg = <0x54>;
111*4882a593Smuzhiyun		pagesize = <16>;
112*4882a593Smuzhiyun	};
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun	pca9555: pca9555@20 {
115*4882a593Smuzhiyun		compatible = "nxp,pca9555";
116*4882a593Smuzhiyun		reg = <0x20>;
117*4882a593Smuzhiyun		gpio-controller;
118*4882a593Smuzhiyun		#gpio-cells = <2>;
119*4882a593Smuzhiyun	};
120*4882a593Smuzhiyun};
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun&dss {
123*4882a593Smuzhiyun	status = "okay";
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun	vdda_video-supply = <&ldoln_reg>;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun	port {
128*4882a593Smuzhiyun		dpi_lcd_out: endpoint {
129*4882a593Smuzhiyun			remote-endpoint = <&lcd_in>;
130*4882a593Smuzhiyun			data-lines = <24>;
131*4882a593Smuzhiyun		};
132*4882a593Smuzhiyun	};
133*4882a593Smuzhiyun};
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun&lcd0 {
136*4882a593Smuzhiyun	pinctrl-names = "default";
137*4882a593Smuzhiyun	pinctrl-0 = <&lcd_pins_default>;
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun	enable-gpios = <&pca9555 14 GPIO_ACTIVE_HIGH
140*4882a593Smuzhiyun			&gpio4 0 GPIO_ACTIVE_HIGH>;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun	port {
143*4882a593Smuzhiyun		lcd_in: endpoint {
144*4882a593Smuzhiyun			remote-endpoint = <&dpi_lcd_out>;
145*4882a593Smuzhiyun			data-lines = <24>;
146*4882a593Smuzhiyun		};
147*4882a593Smuzhiyun	};
148*4882a593Smuzhiyun};
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun&hdmi {
151*4882a593Smuzhiyun	status = "okay";
152*4882a593Smuzhiyun	vdda-supply = <&ldo4_reg>;
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun	pinctrl-names = "default";
155*4882a593Smuzhiyun	pinctrl-0 = <&hdmi_pins>;
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun	port {
158*4882a593Smuzhiyun		hdmi_out: endpoint {
159*4882a593Smuzhiyun			remote-endpoint = <&hdmi_connector_in>;
160*4882a593Smuzhiyun			lanes = <1 0 3 2 5 4 7 6>;
161*4882a593Smuzhiyun		};
162*4882a593Smuzhiyun	};
163*4882a593Smuzhiyun};
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun&hdmi_conn {
166*4882a593Smuzhiyun	pinctrl-names = "default";
167*4882a593Smuzhiyun	pinctrl-0 = <&hdmi_conn_pins>;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun	hpd-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>;
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun	port {
172*4882a593Smuzhiyun		hdmi_connector_in: endpoint {
173*4882a593Smuzhiyun			remote-endpoint = <&hdmi_out>;
174*4882a593Smuzhiyun		};
175*4882a593Smuzhiyun	};
176*4882a593Smuzhiyun};
177