1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Common PRUSS data for TI AM57xx platforms 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun&ocp { 9*4882a593Smuzhiyun pruss1_tm: target-module@4b226000 { 10*4882a593Smuzhiyun compatible = "ti,sysc-pruss", "ti,sysc"; 11*4882a593Smuzhiyun reg = <0x4b226000 0x4>, 12*4882a593Smuzhiyun <0x4b226004 0x4>; 13*4882a593Smuzhiyun reg-names = "rev", "sysc"; 14*4882a593Smuzhiyun ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT | 15*4882a593Smuzhiyun SYSC_PRUSS_SUB_MWAIT)>; 16*4882a593Smuzhiyun ti,sysc-midle = <SYSC_IDLE_FORCE>, 17*4882a593Smuzhiyun <SYSC_IDLE_NO>, 18*4882a593Smuzhiyun <SYSC_IDLE_SMART>; 19*4882a593Smuzhiyun ti,sysc-sidle = <SYSC_IDLE_FORCE>, 20*4882a593Smuzhiyun <SYSC_IDLE_NO>, 21*4882a593Smuzhiyun <SYSC_IDLE_SMART>; 22*4882a593Smuzhiyun /* Domains (P, C): coreaon_pwrdm, l4per2_clkdm */ 23*4882a593Smuzhiyun clocks = <&l4per2_clkctrl DRA7_L4PER2_PRUSS1_CLKCTRL 0>; 24*4882a593Smuzhiyun clock-names = "fck"; 25*4882a593Smuzhiyun #address-cells = <1>; 26*4882a593Smuzhiyun #size-cells = <1>; 27*4882a593Smuzhiyun ranges = <0x00000000 0x4b200000 0x80000>; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun pruss2_tm: target-module@4b2a6000 { 31*4882a593Smuzhiyun compatible = "ti,sysc-pruss", "ti,sysc"; 32*4882a593Smuzhiyun reg = <0x4b2a6000 0x4>, 33*4882a593Smuzhiyun <0x4b2a6004 0x4>; 34*4882a593Smuzhiyun reg-names = "rev", "sysc"; 35*4882a593Smuzhiyun ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT | 36*4882a593Smuzhiyun SYSC_PRUSS_SUB_MWAIT)>; 37*4882a593Smuzhiyun ti,sysc-midle = <SYSC_IDLE_FORCE>, 38*4882a593Smuzhiyun <SYSC_IDLE_NO>, 39*4882a593Smuzhiyun <SYSC_IDLE_SMART>; 40*4882a593Smuzhiyun ti,sysc-sidle = <SYSC_IDLE_FORCE>, 41*4882a593Smuzhiyun <SYSC_IDLE_NO>, 42*4882a593Smuzhiyun <SYSC_IDLE_SMART>; 43*4882a593Smuzhiyun /* Domains (P, C): coreaon_pwrdm, l4per2_clkdm */ 44*4882a593Smuzhiyun clocks = <&l4per2_clkctrl DRA7_L4PER2_PRUSS2_CLKCTRL 0>; 45*4882a593Smuzhiyun clock-names = "fck"; 46*4882a593Smuzhiyun #address-cells = <1>; 47*4882a593Smuzhiyun #size-cells = <1>; 48*4882a593Smuzhiyun ranges = <0x00000000 0x4b280000 0x80000>; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun}; 51