1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/* AM437x GP EVM */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/dts-v1/; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun#include "am4372.dtsi" 11*4882a593Smuzhiyun#include <dt-bindings/pinctrl/am43xx.h> 12*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h> 13*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun/ { 16*4882a593Smuzhiyun model = "TI AM437x GP EVM"; 17*4882a593Smuzhiyun compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43"; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun aliases { 20*4882a593Smuzhiyun display0 = &lcd0; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun chosen { 24*4882a593Smuzhiyun stdout-path = &uart0; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun evm_v3_3d: fixedregulator-v3_3d { 28*4882a593Smuzhiyun compatible = "regulator-fixed"; 29*4882a593Smuzhiyun regulator-name = "evm_v3_3d"; 30*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 31*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 32*4882a593Smuzhiyun enable-active-high; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun vtt_fixed: fixedregulator-vtt { 36*4882a593Smuzhiyun compatible = "regulator-fixed"; 37*4882a593Smuzhiyun regulator-name = "vtt_fixed"; 38*4882a593Smuzhiyun regulator-min-microvolt = <1500000>; 39*4882a593Smuzhiyun regulator-max-microvolt = <1500000>; 40*4882a593Smuzhiyun regulator-always-on; 41*4882a593Smuzhiyun regulator-boot-on; 42*4882a593Smuzhiyun enable-active-high; 43*4882a593Smuzhiyun gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun vmmcwl_fixed: fixedregulator-mmcwl { 47*4882a593Smuzhiyun compatible = "regulator-fixed"; 48*4882a593Smuzhiyun regulator-name = "vmmcwl_fixed"; 49*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 50*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 51*4882a593Smuzhiyun gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>; 52*4882a593Smuzhiyun enable-active-high; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun lcd_bl: backlight { 56*4882a593Smuzhiyun compatible = "pwm-backlight"; 57*4882a593Smuzhiyun pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; 58*4882a593Smuzhiyun brightness-levels = <0 51 53 56 62 75 101 152 255>; 59*4882a593Smuzhiyun default-brightness-level = <8>; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun matrix_keypad: matrix_keypad0 { 63*4882a593Smuzhiyun compatible = "gpio-matrix-keypad"; 64*4882a593Smuzhiyun debounce-delay-ms = <5>; 65*4882a593Smuzhiyun col-scan-delay-us = <2>; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 68*4882a593Smuzhiyun pinctrl-0 = <&matrix_keypad_default>; 69*4882a593Smuzhiyun pinctrl-1 = <&matrix_keypad_sleep>; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun wakeup-source; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun row-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH /* Bank0, pin3 */ 74*4882a593Smuzhiyun &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */ 75*4882a593Smuzhiyun &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */ 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */ 78*4882a593Smuzhiyun &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */ 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun linux,keymap = <0x00000201 /* P1 */ 81*4882a593Smuzhiyun 0x00010202 /* P2 */ 82*4882a593Smuzhiyun 0x01000067 /* UP */ 83*4882a593Smuzhiyun 0x0101006a /* RIGHT */ 84*4882a593Smuzhiyun 0x02000069 /* LEFT */ 85*4882a593Smuzhiyun 0x0201006c>; /* DOWN */ 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun lcd0: display { 89*4882a593Smuzhiyun compatible = "osddisplays,osd070t1718-19ts", "panel-dpi"; 90*4882a593Smuzhiyun label = "lcd"; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun backlight = <&lcd_bl>; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun port { 95*4882a593Smuzhiyun lcd_in: endpoint { 96*4882a593Smuzhiyun remote-endpoint = <&dpi_out>; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun /* fixed 12MHz oscillator */ 102*4882a593Smuzhiyun refclk: oscillator { 103*4882a593Smuzhiyun #clock-cells = <0>; 104*4882a593Smuzhiyun compatible = "fixed-clock"; 105*4882a593Smuzhiyun clock-frequency = <12000000>; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /* fixed 32k external oscillator clock */ 109*4882a593Smuzhiyun clk_32k_rtc: clk_32k_rtc { 110*4882a593Smuzhiyun #clock-cells = <0>; 111*4882a593Smuzhiyun compatible = "fixed-clock"; 112*4882a593Smuzhiyun clock-frequency = <32768>; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun sound0: sound0 { 116*4882a593Smuzhiyun compatible = "simple-audio-card"; 117*4882a593Smuzhiyun simple-audio-card,name = "AM437x-GP-EVM"; 118*4882a593Smuzhiyun simple-audio-card,widgets = 119*4882a593Smuzhiyun "Headphone", "Headphone Jack", 120*4882a593Smuzhiyun "Line", "Line In"; 121*4882a593Smuzhiyun simple-audio-card,routing = 122*4882a593Smuzhiyun "Headphone Jack", "HPLOUT", 123*4882a593Smuzhiyun "Headphone Jack", "HPROUT", 124*4882a593Smuzhiyun "LINE1L", "Line In", 125*4882a593Smuzhiyun "LINE1R", "Line In"; 126*4882a593Smuzhiyun simple-audio-card,format = "dsp_b"; 127*4882a593Smuzhiyun simple-audio-card,bitclock-master = <&sound0_master>; 128*4882a593Smuzhiyun simple-audio-card,frame-master = <&sound0_master>; 129*4882a593Smuzhiyun simple-audio-card,bitclock-inversion; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun simple-audio-card,cpu { 132*4882a593Smuzhiyun sound-dai = <&mcasp1>; 133*4882a593Smuzhiyun system-clock-frequency = <12000000>; 134*4882a593Smuzhiyun }; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun sound0_master: simple-audio-card,codec { 137*4882a593Smuzhiyun sound-dai = <&tlv320aic3106>; 138*4882a593Smuzhiyun system-clock-frequency = <12000000>; 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun beeper: beeper { 143*4882a593Smuzhiyun compatible = "gpio-beeper"; 144*4882a593Smuzhiyun pinctrl-names = "default"; 145*4882a593Smuzhiyun pinctrl-0 = <&beeper_pins_default>; 146*4882a593Smuzhiyun pinctrl-1 = <&beeper_pins_sleep>; 147*4882a593Smuzhiyun gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; 148*4882a593Smuzhiyun }; 149*4882a593Smuzhiyun}; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun&am43xx_pinmux { 152*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 153*4882a593Smuzhiyun pinctrl-0 = <&wlan_pins_default &ddr3_vtt_toggle_default &unused_pins &debugss_pins>; 154*4882a593Smuzhiyun pinctrl-1 = <&wlan_pins_sleep>; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun ddr3_vtt_toggle_default: ddr_vtt_toggle_default { 157*4882a593Smuzhiyun pinctrl-single,pins = < 158*4882a593Smuzhiyun 0x25C (DS0_PULL_UP_DOWN_EN | PIN_OUTPUT_PULLUP | DS0_FORCE_OFF_MODE | MUX_MODE7) /* spi0_cs0.gpio5_7 */ 159*4882a593Smuzhiyun >; 160*4882a593Smuzhiyun }; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun i2c0_pins: i2c0_pins { 163*4882a593Smuzhiyun pinctrl-single,pins = < 164*4882a593Smuzhiyun AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ 165*4882a593Smuzhiyun AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ 166*4882a593Smuzhiyun >; 167*4882a593Smuzhiyun }; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun i2c1_pins: i2c1_pins { 170*4882a593Smuzhiyun pinctrl-single,pins = < 171*4882a593Smuzhiyun AM4372_IOPAD(0x95c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */ 172*4882a593Smuzhiyun AM4372_IOPAD(0x958, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */ 173*4882a593Smuzhiyun >; 174*4882a593Smuzhiyun }; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun mmc1_pins: pinmux_mmc1_pins { 177*4882a593Smuzhiyun pinctrl-single,pins = < 178*4882a593Smuzhiyun AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ 179*4882a593Smuzhiyun >; 180*4882a593Smuzhiyun }; 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun ecap0_pins: backlight_pins { 183*4882a593Smuzhiyun pinctrl-single,pins = < 184*4882a593Smuzhiyun AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ 185*4882a593Smuzhiyun >; 186*4882a593Smuzhiyun }; 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun pixcir_ts_pins: pixcir_ts_pins { 189*4882a593Smuzhiyun pinctrl-single,pins = < 190*4882a593Smuzhiyun AM4372_IOPAD(0xa64, PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */ 191*4882a593Smuzhiyun >; 192*4882a593Smuzhiyun }; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun cpsw_default: cpsw_default { 195*4882a593Smuzhiyun pinctrl-single,pins = < 196*4882a593Smuzhiyun /* Slave 1 */ 197*4882a593Smuzhiyun AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */ 198*4882a593Smuzhiyun AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */ 199*4882a593Smuzhiyun AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */ 200*4882a593Smuzhiyun AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */ 201*4882a593Smuzhiyun AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */ 202*4882a593Smuzhiyun AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */ 203*4882a593Smuzhiyun AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */ 204*4882a593Smuzhiyun AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */ 205*4882a593Smuzhiyun AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */ 206*4882a593Smuzhiyun AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */ 207*4882a593Smuzhiyun AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */ 208*4882a593Smuzhiyun AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */ 209*4882a593Smuzhiyun >; 210*4882a593Smuzhiyun }; 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun cpsw_sleep: cpsw_sleep { 213*4882a593Smuzhiyun pinctrl-single,pins = < 214*4882a593Smuzhiyun /* Slave 1 reset value */ 215*4882a593Smuzhiyun AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) 216*4882a593Smuzhiyun AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) 217*4882a593Smuzhiyun AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7) 218*4882a593Smuzhiyun AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7) 219*4882a593Smuzhiyun AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) 220*4882a593Smuzhiyun AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) 221*4882a593Smuzhiyun AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7) 222*4882a593Smuzhiyun AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7) 223*4882a593Smuzhiyun AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7) 224*4882a593Smuzhiyun AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7) 225*4882a593Smuzhiyun AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) 226*4882a593Smuzhiyun AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) 227*4882a593Smuzhiyun >; 228*4882a593Smuzhiyun }; 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun davinci_mdio_default: davinci_mdio_default { 231*4882a593Smuzhiyun pinctrl-single,pins = < 232*4882a593Smuzhiyun /* MDIO */ 233*4882a593Smuzhiyun AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ 234*4882a593Smuzhiyun AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ 235*4882a593Smuzhiyun >; 236*4882a593Smuzhiyun }; 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun davinci_mdio_sleep: davinci_mdio_sleep { 239*4882a593Smuzhiyun pinctrl-single,pins = < 240*4882a593Smuzhiyun /* MDIO reset value */ 241*4882a593Smuzhiyun AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) 242*4882a593Smuzhiyun AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) 243*4882a593Smuzhiyun >; 244*4882a593Smuzhiyun }; 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun nand_flash_x8: nand_flash_x8 { 247*4882a593Smuzhiyun pinctrl-single,pins = < 248*4882a593Smuzhiyun AM4372_IOPAD(0x800, PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ 249*4882a593Smuzhiyun AM4372_IOPAD(0x804, PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ 250*4882a593Smuzhiyun AM4372_IOPAD(0x808, PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ 251*4882a593Smuzhiyun AM4372_IOPAD(0x80c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ 252*4882a593Smuzhiyun AM4372_IOPAD(0x810, PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ 253*4882a593Smuzhiyun AM4372_IOPAD(0x814, PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ 254*4882a593Smuzhiyun AM4372_IOPAD(0x818, PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ 255*4882a593Smuzhiyun AM4372_IOPAD(0x81c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ 256*4882a593Smuzhiyun AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ 257*4882a593Smuzhiyun AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */ 258*4882a593Smuzhiyun AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ 259*4882a593Smuzhiyun AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ 260*4882a593Smuzhiyun AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ 261*4882a593Smuzhiyun AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ 262*4882a593Smuzhiyun AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ 263*4882a593Smuzhiyun >; 264*4882a593Smuzhiyun }; 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun dss_pins: dss_pins { 267*4882a593Smuzhiyun pinctrl-single,pins = < 268*4882a593Smuzhiyun AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */ 269*4882a593Smuzhiyun AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1) 270*4882a593Smuzhiyun AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1) 271*4882a593Smuzhiyun AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1) 272*4882a593Smuzhiyun AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1) 273*4882a593Smuzhiyun AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1) 274*4882a593Smuzhiyun AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1) 275*4882a593Smuzhiyun AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */ 276*4882a593Smuzhiyun AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ 277*4882a593Smuzhiyun AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0) 278*4882a593Smuzhiyun AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0) 279*4882a593Smuzhiyun AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0) 280*4882a593Smuzhiyun AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0) 281*4882a593Smuzhiyun AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0) 282*4882a593Smuzhiyun AM4372_IOPAD(0x8b8, PIN_OUTPUT_PULLUP | MUX_MODE0) 283*4882a593Smuzhiyun AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0) 284*4882a593Smuzhiyun AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0) 285*4882a593Smuzhiyun AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0) 286*4882a593Smuzhiyun AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0) 287*4882a593Smuzhiyun AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0) 288*4882a593Smuzhiyun AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0) 289*4882a593Smuzhiyun AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0) 290*4882a593Smuzhiyun AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0) 291*4882a593Smuzhiyun AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ 292*4882a593Smuzhiyun AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ 293*4882a593Smuzhiyun AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ 294*4882a593Smuzhiyun AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ 295*4882a593Smuzhiyun AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun >; 298*4882a593Smuzhiyun }; 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun display_mux_pins: display_mux_pins { 301*4882a593Smuzhiyun pinctrl-single,pins = < 302*4882a593Smuzhiyun /* GPIO 5_8 to select LCD / HDMI */ 303*4882a593Smuzhiyun AM4372_IOPAD(0xa38, PIN_OUTPUT_PULLUP | MUX_MODE7) 304*4882a593Smuzhiyun >; 305*4882a593Smuzhiyun }; 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun dcan0_default: dcan0_default_pins { 308*4882a593Smuzhiyun pinctrl-single,pins = < 309*4882a593Smuzhiyun AM4372_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */ 310*4882a593Smuzhiyun AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */ 311*4882a593Smuzhiyun >; 312*4882a593Smuzhiyun }; 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun dcan0_sleep: dcan0_sleep_pins { 315*4882a593Smuzhiyun pinctrl-single,pins = < 316*4882a593Smuzhiyun AM4372_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_ctsn.gpio0_12 */ 317*4882a593Smuzhiyun AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rtsn.gpio0_13 */ 318*4882a593Smuzhiyun >; 319*4882a593Smuzhiyun }; 320*4882a593Smuzhiyun 321*4882a593Smuzhiyun dcan1_default: dcan1_default_pins { 322*4882a593Smuzhiyun pinctrl-single,pins = < 323*4882a593Smuzhiyun AM4372_IOPAD(0x980, PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */ 324*4882a593Smuzhiyun AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */ 325*4882a593Smuzhiyun >; 326*4882a593Smuzhiyun }; 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun dcan1_sleep: dcan1_sleep_pins { 329*4882a593Smuzhiyun pinctrl-single,pins = < 330*4882a593Smuzhiyun AM4372_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_rxd.gpio0_14 */ 331*4882a593Smuzhiyun AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE7) /* uart1_txd.gpio0_15 */ 332*4882a593Smuzhiyun >; 333*4882a593Smuzhiyun }; 334*4882a593Smuzhiyun 335*4882a593Smuzhiyun vpfe0_pins_default: vpfe0_pins_default { 336*4882a593Smuzhiyun pinctrl-single,pins = < 337*4882a593Smuzhiyun AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/ 338*4882a593Smuzhiyun AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/ 339*4882a593Smuzhiyun AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/ 340*4882a593Smuzhiyun AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/ 341*4882a593Smuzhiyun AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/ 342*4882a593Smuzhiyun AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/ 343*4882a593Smuzhiyun AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/ 344*4882a593Smuzhiyun AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/ 345*4882a593Smuzhiyun AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/ 346*4882a593Smuzhiyun AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/ 347*4882a593Smuzhiyun AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/ 348*4882a593Smuzhiyun AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/ 349*4882a593Smuzhiyun AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/ 350*4882a593Smuzhiyun >; 351*4882a593Smuzhiyun }; 352*4882a593Smuzhiyun 353*4882a593Smuzhiyun vpfe0_pins_sleep: vpfe0_pins_sleep { 354*4882a593Smuzhiyun pinctrl-single,pins = < 355*4882a593Smuzhiyun AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/ 356*4882a593Smuzhiyun AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/ 357*4882a593Smuzhiyun AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/ 358*4882a593Smuzhiyun AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/ 359*4882a593Smuzhiyun AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/ 360*4882a593Smuzhiyun AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/ 361*4882a593Smuzhiyun AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/ 362*4882a593Smuzhiyun AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/ 363*4882a593Smuzhiyun AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/ 364*4882a593Smuzhiyun AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/ 365*4882a593Smuzhiyun AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/ 366*4882a593Smuzhiyun AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/ 367*4882a593Smuzhiyun AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/ 368*4882a593Smuzhiyun >; 369*4882a593Smuzhiyun }; 370*4882a593Smuzhiyun 371*4882a593Smuzhiyun vpfe1_pins_default: vpfe1_pins_default { 372*4882a593Smuzhiyun pinctrl-single,pins = < 373*4882a593Smuzhiyun AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/ 374*4882a593Smuzhiyun AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/ 375*4882a593Smuzhiyun AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/ 376*4882a593Smuzhiyun AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/ 377*4882a593Smuzhiyun AM4372_IOPAD(0x9dC, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/ 378*4882a593Smuzhiyun AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/ 379*4882a593Smuzhiyun AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/ 380*4882a593Smuzhiyun AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/ 381*4882a593Smuzhiyun AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/ 382*4882a593Smuzhiyun AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/ 383*4882a593Smuzhiyun AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/ 384*4882a593Smuzhiyun AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/ 385*4882a593Smuzhiyun AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/ 386*4882a593Smuzhiyun >; 387*4882a593Smuzhiyun }; 388*4882a593Smuzhiyun 389*4882a593Smuzhiyun vpfe1_pins_sleep: vpfe1_pins_sleep { 390*4882a593Smuzhiyun pinctrl-single,pins = < 391*4882a593Smuzhiyun AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/ 392*4882a593Smuzhiyun AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/ 393*4882a593Smuzhiyun AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/ 394*4882a593Smuzhiyun AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/ 395*4882a593Smuzhiyun AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/ 396*4882a593Smuzhiyun AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/ 397*4882a593Smuzhiyun AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/ 398*4882a593Smuzhiyun AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/ 399*4882a593Smuzhiyun AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/ 400*4882a593Smuzhiyun AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/ 401*4882a593Smuzhiyun AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/ 402*4882a593Smuzhiyun AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/ 403*4882a593Smuzhiyun AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/ 404*4882a593Smuzhiyun >; 405*4882a593Smuzhiyun }; 406*4882a593Smuzhiyun 407*4882a593Smuzhiyun mmc3_pins_default: pinmux_mmc3_pins_default { 408*4882a593Smuzhiyun pinctrl-single,pins = < 409*4882a593Smuzhiyun AM4372_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk */ 410*4882a593Smuzhiyun AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */ 411*4882a593Smuzhiyun AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */ 412*4882a593Smuzhiyun AM4372_IOPAD(0x848, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */ 413*4882a593Smuzhiyun AM4372_IOPAD(0x84c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */ 414*4882a593Smuzhiyun AM4372_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be1n.mmc2_dat3 */ 415*4882a593Smuzhiyun >; 416*4882a593Smuzhiyun }; 417*4882a593Smuzhiyun 418*4882a593Smuzhiyun mmc3_pins_sleep: pinmux_mmc3_pins_sleep { 419*4882a593Smuzhiyun pinctrl-single,pins = < 420*4882a593Smuzhiyun AM4372_IOPAD(0x88c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_clk.mmc2_clk */ 421*4882a593Smuzhiyun AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.mmc2_cmd */ 422*4882a593Smuzhiyun AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a1.mmc2_dat0 */ 423*4882a593Smuzhiyun AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a2.mmc2_dat1 */ 424*4882a593Smuzhiyun AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a3.mmc2_dat2 */ 425*4882a593Smuzhiyun AM4372_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_be1n.mmc2_dat3 */ 426*4882a593Smuzhiyun >; 427*4882a593Smuzhiyun }; 428*4882a593Smuzhiyun 429*4882a593Smuzhiyun wlan_pins_default: pinmux_wlan_pins_default { 430*4882a593Smuzhiyun pinctrl-single,pins = < 431*4882a593Smuzhiyun AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */ 432*4882a593Smuzhiyun AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/ 433*4882a593Smuzhiyun AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/ 434*4882a593Smuzhiyun >; 435*4882a593Smuzhiyun }; 436*4882a593Smuzhiyun 437*4882a593Smuzhiyun wlan_pins_sleep: pinmux_wlan_pins_sleep { 438*4882a593Smuzhiyun pinctrl-single,pins = < 439*4882a593Smuzhiyun AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a4.gpio1_20 WL_EN */ 440*4882a593Smuzhiyun AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7) /* gpmc_a7.gpio1_23 WL_IRQ*/ 441*4882a593Smuzhiyun AM4372_IOPAD(0x840, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a0.gpio1_16 BT_EN*/ 442*4882a593Smuzhiyun >; 443*4882a593Smuzhiyun }; 444*4882a593Smuzhiyun 445*4882a593Smuzhiyun uart3_pins: uart3_pins { 446*4882a593Smuzhiyun pinctrl-single,pins = < 447*4882a593Smuzhiyun AM4372_IOPAD(0xa28, PIN_INPUT | MUX_MODE0) /* uart3_rxd.uart3_rxd */ 448*4882a593Smuzhiyun AM4372_IOPAD(0xa2c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */ 449*4882a593Smuzhiyun AM4372_IOPAD(0xa30, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_ctsn.uart3_ctsn */ 450*4882a593Smuzhiyun AM4372_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */ 451*4882a593Smuzhiyun >; 452*4882a593Smuzhiyun }; 453*4882a593Smuzhiyun 454*4882a593Smuzhiyun mcasp1_pins: mcasp1_pins { 455*4882a593Smuzhiyun pinctrl-single,pins = < 456*4882a593Smuzhiyun AM4372_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ 457*4882a593Smuzhiyun AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ 458*4882a593Smuzhiyun AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ 459*4882a593Smuzhiyun AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ 460*4882a593Smuzhiyun >; 461*4882a593Smuzhiyun }; 462*4882a593Smuzhiyun 463*4882a593Smuzhiyun mcasp1_sleep_pins: mcasp1_sleep_pins { 464*4882a593Smuzhiyun pinctrl-single,pins = < 465*4882a593Smuzhiyun AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7) 466*4882a593Smuzhiyun AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) 467*4882a593Smuzhiyun AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) 468*4882a593Smuzhiyun AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) 469*4882a593Smuzhiyun >; 470*4882a593Smuzhiyun }; 471*4882a593Smuzhiyun 472*4882a593Smuzhiyun gpio0_pins: gpio0_pins { 473*4882a593Smuzhiyun pinctrl-single,pins = < 474*4882a593Smuzhiyun AM4372_IOPAD(0xa6c, PIN_OUTPUT | MUX_MODE9) /* spi2_cs0.gpio0_23 SEL_eMMCorNANDn */ 475*4882a593Smuzhiyun >; 476*4882a593Smuzhiyun }; 477*4882a593Smuzhiyun 478*4882a593Smuzhiyun emmc_pins_default: emmc_pins_default { 479*4882a593Smuzhiyun pinctrl-single,pins = < 480*4882a593Smuzhiyun AM4372_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ 481*4882a593Smuzhiyun AM4372_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ 482*4882a593Smuzhiyun AM4372_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ 483*4882a593Smuzhiyun AM4372_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ 484*4882a593Smuzhiyun AM4372_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ 485*4882a593Smuzhiyun AM4372_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ 486*4882a593Smuzhiyun AM4372_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ 487*4882a593Smuzhiyun AM4372_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ 488*4882a593Smuzhiyun AM4372_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ 489*4882a593Smuzhiyun AM4372_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ 490*4882a593Smuzhiyun >; 491*4882a593Smuzhiyun }; 492*4882a593Smuzhiyun 493*4882a593Smuzhiyun emmc_pins_sleep: emmc_pins_sleep { 494*4882a593Smuzhiyun pinctrl-single,pins = < 495*4882a593Smuzhiyun AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad0.gpio1_0 */ 496*4882a593Smuzhiyun AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad1.gpio1_1 */ 497*4882a593Smuzhiyun AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad2.gpio1_2 */ 498*4882a593Smuzhiyun AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad3.gpio1_3 */ 499*4882a593Smuzhiyun AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */ 500*4882a593Smuzhiyun AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */ 501*4882a593Smuzhiyun AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */ 502*4882a593Smuzhiyun AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */ 503*4882a593Smuzhiyun AM4372_IOPAD(0x880, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn1.gpio1_30 */ 504*4882a593Smuzhiyun AM4372_IOPAD(0x884, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn2.gpio1_31 */ 505*4882a593Smuzhiyun >; 506*4882a593Smuzhiyun }; 507*4882a593Smuzhiyun 508*4882a593Smuzhiyun beeper_pins_default: beeper_pins_default { 509*4882a593Smuzhiyun pinctrl-single,pins = < 510*4882a593Smuzhiyun AM4372_IOPAD(0x9e0, PIN_OUTPUT_PULLUP | MUX_MODE7) /* cam1_field.gpio4_12 */ 511*4882a593Smuzhiyun >; 512*4882a593Smuzhiyun }; 513*4882a593Smuzhiyun 514*4882a593Smuzhiyun beeper_pins_sleep: beeper_pins_sleep { 515*4882a593Smuzhiyun pinctrl-single,pins = < 516*4882a593Smuzhiyun AM4372_IOPAD(0x9e0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* cam1_field.gpio4_12 */ 517*4882a593Smuzhiyun >; 518*4882a593Smuzhiyun }; 519*4882a593Smuzhiyun 520*4882a593Smuzhiyun unused_pins: unused_pins { 521*4882a593Smuzhiyun pinctrl-single,pins = < 522*4882a593Smuzhiyun AM4372_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) 523*4882a593Smuzhiyun AM4372_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7) 524*4882a593Smuzhiyun AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7) 525*4882a593Smuzhiyun AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) 526*4882a593Smuzhiyun AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) 527*4882a593Smuzhiyun AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) 528*4882a593Smuzhiyun AM4372_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE7) 529*4882a593Smuzhiyun AM4372_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE7) 530*4882a593Smuzhiyun AM4372_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE7) 531*4882a593Smuzhiyun AM4372_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE7) 532*4882a593Smuzhiyun AM4372_IOPAD(0x99c, PIN_INPUT_PULLDOWN | MUX_MODE7) 533*4882a593Smuzhiyun AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7) 534*4882a593Smuzhiyun AM4372_IOPAD(0xa3c, PIN_INPUT | PULL_DISABLE | MUX_MODE7) 535*4882a593Smuzhiyun AM4372_IOPAD(0xa40, PIN_INPUT_PULLDOWN | MUX_MODE7) 536*4882a593Smuzhiyun AM4372_IOPAD(0xa44, PIN_INPUT_PULLDOWN | MUX_MODE7) 537*4882a593Smuzhiyun AM4372_IOPAD(0xa48, PIN_INPUT_PULLDOWN | MUX_MODE7) 538*4882a593Smuzhiyun AM4372_IOPAD(0xa4c, PIN_INPUT_PULLDOWN | MUX_MODE7) 539*4882a593Smuzhiyun AM4372_IOPAD(0xa50, PIN_INPUT_PULLDOWN | MUX_MODE7) 540*4882a593Smuzhiyun AM4372_IOPAD(0xa54, PIN_INPUT | PULL_DISABLE | MUX_MODE7) 541*4882a593Smuzhiyun AM4372_IOPAD(0xa58, PIN_INPUT_PULLDOWN | MUX_MODE7) 542*4882a593Smuzhiyun AM4372_IOPAD(0xa60, PIN_INPUT | PULL_DISABLE | MUX_MODE7) 543*4882a593Smuzhiyun AM4372_IOPAD(0xa68, PIN_INPUT_PULLDOWN | MUX_MODE7) 544*4882a593Smuzhiyun AM4372_IOPAD(0xa70, PIN_INPUT_PULLDOWN | MUX_MODE7) 545*4882a593Smuzhiyun AM4372_IOPAD(0xa78, PIN_INPUT_PULLDOWN | MUX_MODE7) 546*4882a593Smuzhiyun AM4372_IOPAD(0xa7c, PIN_INPUT | PULL_DISABLE) 547*4882a593Smuzhiyun AM4372_IOPAD(0xac8, PIN_INPUT_PULLDOWN) 548*4882a593Smuzhiyun AM4372_IOPAD(0xad4, PIN_INPUT_PULLDOWN) 549*4882a593Smuzhiyun AM4372_IOPAD(0xad8, PIN_INPUT_PULLDOWN | MUX_MODE7) 550*4882a593Smuzhiyun AM4372_IOPAD(0xadc, PIN_INPUT_PULLDOWN | MUX_MODE7) 551*4882a593Smuzhiyun AM4372_IOPAD(0xae0, PIN_INPUT_PULLDOWN | MUX_MODE7) 552*4882a593Smuzhiyun AM4372_IOPAD(0xae4, PIN_INPUT_PULLDOWN | MUX_MODE7) 553*4882a593Smuzhiyun AM4372_IOPAD(0xae8, PIN_INPUT_PULLDOWN | MUX_MODE7) 554*4882a593Smuzhiyun AM4372_IOPAD(0xaec, PIN_INPUT_PULLDOWN | MUX_MODE7) 555*4882a593Smuzhiyun AM4372_IOPAD(0xaf0, PIN_INPUT_PULLDOWN | MUX_MODE7) 556*4882a593Smuzhiyun AM4372_IOPAD(0xaf4, PIN_INPUT_PULLDOWN | MUX_MODE7) 557*4882a593Smuzhiyun AM4372_IOPAD(0xaf8, PIN_INPUT_PULLDOWN | MUX_MODE7) 558*4882a593Smuzhiyun AM4372_IOPAD(0xafc, PIN_INPUT_PULLDOWN | MUX_MODE7) 559*4882a593Smuzhiyun AM4372_IOPAD(0xb00, PIN_INPUT_PULLDOWN | MUX_MODE7) 560*4882a593Smuzhiyun AM4372_IOPAD(0xb04, PIN_INPUT_PULLDOWN | MUX_MODE7) 561*4882a593Smuzhiyun AM4372_IOPAD(0xb08, PIN_INPUT_PULLDOWN | MUX_MODE7) 562*4882a593Smuzhiyun AM4372_IOPAD(0xb0c, PIN_INPUT_PULLDOWN | MUX_MODE7) 563*4882a593Smuzhiyun AM4372_IOPAD(0xb10, PIN_INPUT_PULLDOWN | MUX_MODE7) 564*4882a593Smuzhiyun AM4372_IOPAD(0xb14, PIN_INPUT_PULLDOWN | MUX_MODE7) 565*4882a593Smuzhiyun AM4372_IOPAD(0xb18, PIN_INPUT_PULLDOWN | MUX_MODE7) 566*4882a593Smuzhiyun >; 567*4882a593Smuzhiyun }; 568*4882a593Smuzhiyun 569*4882a593Smuzhiyun debugss_pins: pinmux_debugss_pins { 570*4882a593Smuzhiyun pinctrl-single,pins = < 571*4882a593Smuzhiyun AM4372_IOPAD(0xa90, PIN_INPUT_PULLDOWN) 572*4882a593Smuzhiyun AM4372_IOPAD(0xa94, PIN_INPUT_PULLDOWN) 573*4882a593Smuzhiyun AM4372_IOPAD(0xa98, PIN_INPUT_PULLDOWN) 574*4882a593Smuzhiyun AM4372_IOPAD(0xa9c, PIN_INPUT_PULLDOWN) 575*4882a593Smuzhiyun AM4372_IOPAD(0xaa0, PIN_INPUT_PULLDOWN) 576*4882a593Smuzhiyun AM4372_IOPAD(0xaa4, PIN_INPUT_PULLDOWN) 577*4882a593Smuzhiyun AM4372_IOPAD(0xaa8, PIN_INPUT_PULLDOWN) 578*4882a593Smuzhiyun >; 579*4882a593Smuzhiyun }; 580*4882a593Smuzhiyun 581*4882a593Smuzhiyun uart0_pins_default: uart0_pins_default { 582*4882a593Smuzhiyun pinctrl-single,pins = < 583*4882a593Smuzhiyun AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */ 584*4882a593Smuzhiyun AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */ 585*4882a593Smuzhiyun AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */ 586*4882a593Smuzhiyun AM4372_IOPAD(0x974, PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */ 587*4882a593Smuzhiyun >; 588*4882a593Smuzhiyun }; 589*4882a593Smuzhiyun 590*4882a593Smuzhiyun uart0_pins_sleep: uart0_pins_sleep { 591*4882a593Smuzhiyun pinctrl-single,pins = < 592*4882a593Smuzhiyun AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* uart0_ctsn.uart0_ctsn */ 593*4882a593Smuzhiyun AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* uart0_rtsn.uart0_rtsn */ 594*4882a593Smuzhiyun AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */ 595*4882a593Smuzhiyun AM4372_IOPAD(0x974, PIN_INPUT_PULLDOWN | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */ 596*4882a593Smuzhiyun >; 597*4882a593Smuzhiyun }; 598*4882a593Smuzhiyun 599*4882a593Smuzhiyun matrix_keypad_default: matrix_keypad_default { 600*4882a593Smuzhiyun pinctrl-single,pins = < 601*4882a593Smuzhiyun AM4372_IOPAD(0x9a4, PIN_OUTPUT | MUX_MODE7) 602*4882a593Smuzhiyun AM4372_IOPAD(0x9a8, PIN_OUTPUT | MUX_MODE7) 603*4882a593Smuzhiyun AM4372_IOPAD(0x9ac, PIN_INPUT | PULL_DISABLE | MUX_MODE9) 604*4882a593Smuzhiyun AM4372_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0) 605*4882a593Smuzhiyun >; 606*4882a593Smuzhiyun }; 607*4882a593Smuzhiyun 608*4882a593Smuzhiyun matrix_keypad_sleep: matrix_keypad_sleep { 609*4882a593Smuzhiyun pinctrl-single,pins = < 610*4882a593Smuzhiyun AM4372_IOPAD(0x9a4, PULL_UP | MUX_MODE7) 611*4882a593Smuzhiyun AM4372_IOPAD(0x9a8, PULL_UP | MUX_MODE7) 612*4882a593Smuzhiyun AM4372_IOPAD(0x9ac, PIN_INPUT | PULL_DISABLE | MUX_MODE9) 613*4882a593Smuzhiyun AM4372_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0) 614*4882a593Smuzhiyun >; 615*4882a593Smuzhiyun }; 616*4882a593Smuzhiyun}; 617*4882a593Smuzhiyun 618*4882a593Smuzhiyun&uart0 { 619*4882a593Smuzhiyun status = "okay"; 620*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 621*4882a593Smuzhiyun pinctrl-0 = <&uart0_pins_default>; 622*4882a593Smuzhiyun pinctrl-1 = <&uart0_pins_sleep>; 623*4882a593Smuzhiyun}; 624*4882a593Smuzhiyun 625*4882a593Smuzhiyun&i2c0 { 626*4882a593Smuzhiyun status = "okay"; 627*4882a593Smuzhiyun pinctrl-names = "default"; 628*4882a593Smuzhiyun pinctrl-0 = <&i2c0_pins>; 629*4882a593Smuzhiyun clock-frequency = <100000>; 630*4882a593Smuzhiyun 631*4882a593Smuzhiyun tps65218: tps65218@24 { 632*4882a593Smuzhiyun reg = <0x24>; 633*4882a593Smuzhiyun compatible = "ti,tps65218"; 634*4882a593Smuzhiyun interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* NMIn */ 635*4882a593Smuzhiyun interrupt-controller; 636*4882a593Smuzhiyun #interrupt-cells = <2>; 637*4882a593Smuzhiyun 638*4882a593Smuzhiyun dcdc1: regulator-dcdc1 { 639*4882a593Smuzhiyun regulator-name = "vdd_core"; 640*4882a593Smuzhiyun regulator-min-microvolt = <912000>; 641*4882a593Smuzhiyun regulator-max-microvolt = <1144000>; 642*4882a593Smuzhiyun regulator-boot-on; 643*4882a593Smuzhiyun regulator-always-on; 644*4882a593Smuzhiyun }; 645*4882a593Smuzhiyun 646*4882a593Smuzhiyun dcdc2: regulator-dcdc2 { 647*4882a593Smuzhiyun regulator-name = "vdd_mpu"; 648*4882a593Smuzhiyun regulator-min-microvolt = <912000>; 649*4882a593Smuzhiyun regulator-max-microvolt = <1378000>; 650*4882a593Smuzhiyun regulator-boot-on; 651*4882a593Smuzhiyun regulator-always-on; 652*4882a593Smuzhiyun }; 653*4882a593Smuzhiyun 654*4882a593Smuzhiyun dcdc3: regulator-dcdc3 { 655*4882a593Smuzhiyun regulator-name = "vdcdc3"; 656*4882a593Smuzhiyun regulator-boot-on; 657*4882a593Smuzhiyun regulator-always-on; 658*4882a593Smuzhiyun regulator-state-mem { 659*4882a593Smuzhiyun regulator-on-in-suspend; 660*4882a593Smuzhiyun }; 661*4882a593Smuzhiyun regulator-state-disk { 662*4882a593Smuzhiyun regulator-off-in-suspend; 663*4882a593Smuzhiyun }; 664*4882a593Smuzhiyun }; 665*4882a593Smuzhiyun 666*4882a593Smuzhiyun dcdc5: regulator-dcdc5 { 667*4882a593Smuzhiyun regulator-name = "v1_0bat"; 668*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 669*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 670*4882a593Smuzhiyun regulator-boot-on; 671*4882a593Smuzhiyun regulator-always-on; 672*4882a593Smuzhiyun regulator-state-mem { 673*4882a593Smuzhiyun regulator-on-in-suspend; 674*4882a593Smuzhiyun }; 675*4882a593Smuzhiyun }; 676*4882a593Smuzhiyun 677*4882a593Smuzhiyun dcdc6: regulator-dcdc6 { 678*4882a593Smuzhiyun regulator-name = "v1_8bat"; 679*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 680*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 681*4882a593Smuzhiyun regulator-boot-on; 682*4882a593Smuzhiyun regulator-always-on; 683*4882a593Smuzhiyun regulator-state-mem { 684*4882a593Smuzhiyun regulator-on-in-suspend; 685*4882a593Smuzhiyun }; 686*4882a593Smuzhiyun }; 687*4882a593Smuzhiyun 688*4882a593Smuzhiyun ldo1: regulator-ldo1 { 689*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 690*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 691*4882a593Smuzhiyun regulator-boot-on; 692*4882a593Smuzhiyun regulator-always-on; 693*4882a593Smuzhiyun }; 694*4882a593Smuzhiyun }; 695*4882a593Smuzhiyun 696*4882a593Smuzhiyun ov2659@30 { 697*4882a593Smuzhiyun compatible = "ovti,ov2659"; 698*4882a593Smuzhiyun reg = <0x30>; 699*4882a593Smuzhiyun 700*4882a593Smuzhiyun clocks = <&refclk 0>; 701*4882a593Smuzhiyun clock-names = "xvclk"; 702*4882a593Smuzhiyun 703*4882a593Smuzhiyun port { 704*4882a593Smuzhiyun ov2659_0: endpoint { 705*4882a593Smuzhiyun remote-endpoint = <&vpfe1_ep>; 706*4882a593Smuzhiyun link-frequencies = /bits/ 64 <70000000>; 707*4882a593Smuzhiyun }; 708*4882a593Smuzhiyun }; 709*4882a593Smuzhiyun }; 710*4882a593Smuzhiyun}; 711*4882a593Smuzhiyun 712*4882a593Smuzhiyun&i2c1 { 713*4882a593Smuzhiyun status = "okay"; 714*4882a593Smuzhiyun pinctrl-names = "default"; 715*4882a593Smuzhiyun pinctrl-0 = <&i2c1_pins>; 716*4882a593Smuzhiyun pixcir_ts@5c { 717*4882a593Smuzhiyun compatible = "pixcir,pixcir_tangoc"; 718*4882a593Smuzhiyun pinctrl-names = "default"; 719*4882a593Smuzhiyun pinctrl-0 = <&pixcir_ts_pins>; 720*4882a593Smuzhiyun reg = <0x5c>; 721*4882a593Smuzhiyun 722*4882a593Smuzhiyun attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 723*4882a593Smuzhiyun 724*4882a593Smuzhiyun /* 725*4882a593Smuzhiyun * 0x264 represents the offset of padconf register of 726*4882a593Smuzhiyun * gpio3_22 from am43xx_pinmux base. 727*4882a593Smuzhiyun */ 728*4882a593Smuzhiyun interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>, 729*4882a593Smuzhiyun <&am43xx_pinmux 0x264>; 730*4882a593Smuzhiyun interrupt-names = "tsc", "wakeup"; 731*4882a593Smuzhiyun 732*4882a593Smuzhiyun touchscreen-size-x = <1024>; 733*4882a593Smuzhiyun touchscreen-size-y = <600>; 734*4882a593Smuzhiyun wakeup-source; 735*4882a593Smuzhiyun }; 736*4882a593Smuzhiyun 737*4882a593Smuzhiyun ov2659@30 { 738*4882a593Smuzhiyun compatible = "ovti,ov2659"; 739*4882a593Smuzhiyun reg = <0x30>; 740*4882a593Smuzhiyun 741*4882a593Smuzhiyun clocks = <&refclk 0>; 742*4882a593Smuzhiyun clock-names = "xvclk"; 743*4882a593Smuzhiyun 744*4882a593Smuzhiyun port { 745*4882a593Smuzhiyun ov2659_1: endpoint { 746*4882a593Smuzhiyun remote-endpoint = <&vpfe0_ep>; 747*4882a593Smuzhiyun link-frequencies = /bits/ 64 <70000000>; 748*4882a593Smuzhiyun }; 749*4882a593Smuzhiyun }; 750*4882a593Smuzhiyun }; 751*4882a593Smuzhiyun 752*4882a593Smuzhiyun tlv320aic3106: tlv320aic3106@1b { 753*4882a593Smuzhiyun #sound-dai-cells = <0>; 754*4882a593Smuzhiyun compatible = "ti,tlv320aic3106"; 755*4882a593Smuzhiyun reg = <0x1b>; 756*4882a593Smuzhiyun status = "okay"; 757*4882a593Smuzhiyun 758*4882a593Smuzhiyun /* Regulators */ 759*4882a593Smuzhiyun IOVDD-supply = <&evm_v3_3d>; /* V3_3D -> <tps63031> EN: V1_8D -> VBAT */ 760*4882a593Smuzhiyun AVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */ 761*4882a593Smuzhiyun DRVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */ 762*4882a593Smuzhiyun DVDD-supply = <&ldo1>; /* V1_8D -> LDO1 */ 763*4882a593Smuzhiyun }; 764*4882a593Smuzhiyun}; 765*4882a593Smuzhiyun 766*4882a593Smuzhiyun&epwmss0 { 767*4882a593Smuzhiyun status = "okay"; 768*4882a593Smuzhiyun}; 769*4882a593Smuzhiyun 770*4882a593Smuzhiyun&tscadc { 771*4882a593Smuzhiyun status = "okay"; 772*4882a593Smuzhiyun 773*4882a593Smuzhiyun adc { 774*4882a593Smuzhiyun ti,adc-channels = <0 1 2 3 4 5 6 7>; 775*4882a593Smuzhiyun }; 776*4882a593Smuzhiyun}; 777*4882a593Smuzhiyun 778*4882a593Smuzhiyun&ecap0 { 779*4882a593Smuzhiyun status = "okay"; 780*4882a593Smuzhiyun pinctrl-names = "default"; 781*4882a593Smuzhiyun pinctrl-0 = <&ecap0_pins>; 782*4882a593Smuzhiyun}; 783*4882a593Smuzhiyun 784*4882a593Smuzhiyun&gpio0 { 785*4882a593Smuzhiyun pinctrl-names = "default"; 786*4882a593Smuzhiyun pinctrl-0 = <&gpio0_pins>; 787*4882a593Smuzhiyun status = "okay"; 788*4882a593Smuzhiyun 789*4882a593Smuzhiyun p23 { 790*4882a593Smuzhiyun gpio-hog; 791*4882a593Smuzhiyun gpios = <23 GPIO_ACTIVE_HIGH>; 792*4882a593Smuzhiyun /* SelEMMCorNAND selects between eMMC and NAND: 793*4882a593Smuzhiyun * Low: NAND 794*4882a593Smuzhiyun * High: eMMC 795*4882a593Smuzhiyun * When changing this line make sure the newly 796*4882a593Smuzhiyun * selected device node is enabled and the previously 797*4882a593Smuzhiyun * selected device node is disabled. 798*4882a593Smuzhiyun */ 799*4882a593Smuzhiyun output-low; 800*4882a593Smuzhiyun line-name = "SelEMMCorNAND"; 801*4882a593Smuzhiyun }; 802*4882a593Smuzhiyun}; 803*4882a593Smuzhiyun 804*4882a593Smuzhiyun&gpio1 { 805*4882a593Smuzhiyun status = "okay"; 806*4882a593Smuzhiyun}; 807*4882a593Smuzhiyun 808*4882a593Smuzhiyun&gpio3 { 809*4882a593Smuzhiyun status = "okay"; 810*4882a593Smuzhiyun}; 811*4882a593Smuzhiyun 812*4882a593Smuzhiyun&gpio4 { 813*4882a593Smuzhiyun status = "okay"; 814*4882a593Smuzhiyun}; 815*4882a593Smuzhiyun 816*4882a593Smuzhiyun&gpio5_target { 817*4882a593Smuzhiyun ti,no-reset-on-init; 818*4882a593Smuzhiyun}; 819*4882a593Smuzhiyun 820*4882a593Smuzhiyun&gpio5 { 821*4882a593Smuzhiyun pinctrl-names = "default"; 822*4882a593Smuzhiyun pinctrl-0 = <&display_mux_pins>; 823*4882a593Smuzhiyun status = "okay"; 824*4882a593Smuzhiyun 825*4882a593Smuzhiyun p8 { 826*4882a593Smuzhiyun /* 827*4882a593Smuzhiyun * SelLCDorHDMI selects between display and audio paths: 828*4882a593Smuzhiyun * Low: HDMI display with audio via HDMI 829*4882a593Smuzhiyun * High: LCD display with analog audio via aic3111 codec 830*4882a593Smuzhiyun */ 831*4882a593Smuzhiyun gpio-hog; 832*4882a593Smuzhiyun gpios = <8 GPIO_ACTIVE_HIGH>; 833*4882a593Smuzhiyun output-high; 834*4882a593Smuzhiyun line-name = "SelLCDorHDMI"; 835*4882a593Smuzhiyun }; 836*4882a593Smuzhiyun}; 837*4882a593Smuzhiyun 838*4882a593Smuzhiyun&mmc1 { 839*4882a593Smuzhiyun status = "okay"; 840*4882a593Smuzhiyun vmmc-supply = <&evm_v3_3d>; 841*4882a593Smuzhiyun bus-width = <4>; 842*4882a593Smuzhiyun pinctrl-names = "default"; 843*4882a593Smuzhiyun pinctrl-0 = <&mmc1_pins>; 844*4882a593Smuzhiyun cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; 845*4882a593Smuzhiyun}; 846*4882a593Smuzhiyun 847*4882a593Smuzhiyun/* eMMC sits on mmc2 */ 848*4882a593Smuzhiyun&mmc2 { 849*4882a593Smuzhiyun /* 850*4882a593Smuzhiyun * When enabling eMMC, disable GPMC/NAND and set 851*4882a593Smuzhiyun * SelEMMCorNAND to output-high 852*4882a593Smuzhiyun */ 853*4882a593Smuzhiyun status = "disabled"; 854*4882a593Smuzhiyun vmmc-supply = <&evm_v3_3d>; 855*4882a593Smuzhiyun bus-width = <8>; 856*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 857*4882a593Smuzhiyun pinctrl-0 = <&emmc_pins_default>; 858*4882a593Smuzhiyun pinctrl-1 = <&emmc_pins_sleep>; 859*4882a593Smuzhiyun non-removable; 860*4882a593Smuzhiyun}; 861*4882a593Smuzhiyun 862*4882a593Smuzhiyun&mmc3 { 863*4882a593Smuzhiyun status = "okay"; 864*4882a593Smuzhiyun /* these are on the crossbar and are outlined in the 865*4882a593Smuzhiyun xbar-event-map element */ 866*4882a593Smuzhiyun dmas = <&edma_xbar 30 0 1>, 867*4882a593Smuzhiyun <&edma_xbar 31 0 2>; 868*4882a593Smuzhiyun dma-names = "tx", "rx"; 869*4882a593Smuzhiyun vmmc-supply = <&vmmcwl_fixed>; 870*4882a593Smuzhiyun bus-width = <4>; 871*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 872*4882a593Smuzhiyun pinctrl-0 = <&mmc3_pins_default>; 873*4882a593Smuzhiyun pinctrl-1 = <&mmc3_pins_sleep>; 874*4882a593Smuzhiyun cap-power-off-card; 875*4882a593Smuzhiyun keep-power-in-suspend; 876*4882a593Smuzhiyun non-removable; 877*4882a593Smuzhiyun 878*4882a593Smuzhiyun #address-cells = <1>; 879*4882a593Smuzhiyun #size-cells = <0>; 880*4882a593Smuzhiyun wlcore: wlcore@0 { 881*4882a593Smuzhiyun compatible = "ti,wl1835"; 882*4882a593Smuzhiyun reg = <2>; 883*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 884*4882a593Smuzhiyun interrupts = <23 IRQ_TYPE_EDGE_RISING>; 885*4882a593Smuzhiyun }; 886*4882a593Smuzhiyun}; 887*4882a593Smuzhiyun 888*4882a593Smuzhiyun&uart3 { 889*4882a593Smuzhiyun status = "okay"; 890*4882a593Smuzhiyun pinctrl-names = "default"; 891*4882a593Smuzhiyun pinctrl-0 = <&uart3_pins>; 892*4882a593Smuzhiyun}; 893*4882a593Smuzhiyun 894*4882a593Smuzhiyun&usb2_phy1 { 895*4882a593Smuzhiyun status = "okay"; 896*4882a593Smuzhiyun}; 897*4882a593Smuzhiyun 898*4882a593Smuzhiyun&usb1 { 899*4882a593Smuzhiyun dr_mode = "otg"; 900*4882a593Smuzhiyun status = "okay"; 901*4882a593Smuzhiyun}; 902*4882a593Smuzhiyun 903*4882a593Smuzhiyun&usb2_phy2 { 904*4882a593Smuzhiyun status = "okay"; 905*4882a593Smuzhiyun}; 906*4882a593Smuzhiyun 907*4882a593Smuzhiyun&usb2 { 908*4882a593Smuzhiyun dr_mode = "host"; 909*4882a593Smuzhiyun status = "okay"; 910*4882a593Smuzhiyun}; 911*4882a593Smuzhiyun 912*4882a593Smuzhiyun&mac_sw { 913*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 914*4882a593Smuzhiyun pinctrl-0 = <&cpsw_default>; 915*4882a593Smuzhiyun pinctrl-1 = <&cpsw_sleep>; 916*4882a593Smuzhiyun status = "okay"; 917*4882a593Smuzhiyun}; 918*4882a593Smuzhiyun 919*4882a593Smuzhiyun&davinci_mdio_sw { 920*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 921*4882a593Smuzhiyun pinctrl-0 = <&davinci_mdio_default>; 922*4882a593Smuzhiyun pinctrl-1 = <&davinci_mdio_sleep>; 923*4882a593Smuzhiyun 924*4882a593Smuzhiyun ethphy0: ethernet-phy@0 { 925*4882a593Smuzhiyun reg = <0>; 926*4882a593Smuzhiyun }; 927*4882a593Smuzhiyun}; 928*4882a593Smuzhiyun 929*4882a593Smuzhiyun&cpsw_port1 { 930*4882a593Smuzhiyun phy-handle = <ðphy0>; 931*4882a593Smuzhiyun phy-mode = "rgmii-rxid"; 932*4882a593Smuzhiyun ti,dual-emac-pvid = <1>; 933*4882a593Smuzhiyun}; 934*4882a593Smuzhiyun 935*4882a593Smuzhiyun&cpsw_port2 { 936*4882a593Smuzhiyun status = "disabled"; 937*4882a593Smuzhiyun}; 938*4882a593Smuzhiyun 939*4882a593Smuzhiyun&elm { 940*4882a593Smuzhiyun status = "okay"; 941*4882a593Smuzhiyun}; 942*4882a593Smuzhiyun 943*4882a593Smuzhiyun&gpmc { 944*4882a593Smuzhiyun /* 945*4882a593Smuzhiyun * When enabling GPMC, disable eMMC and set 946*4882a593Smuzhiyun * SelEMMCorNAND to output-low 947*4882a593Smuzhiyun */ 948*4882a593Smuzhiyun status = "okay"; 949*4882a593Smuzhiyun pinctrl-names = "default"; 950*4882a593Smuzhiyun pinctrl-0 = <&nand_flash_x8>; 951*4882a593Smuzhiyun ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */ 952*4882a593Smuzhiyun nand@0,0 { 953*4882a593Smuzhiyun compatible = "ti,omap2-nand"; 954*4882a593Smuzhiyun reg = <0 0 4>; /* device IO registers */ 955*4882a593Smuzhiyun interrupt-parent = <&gpmc>; 956*4882a593Smuzhiyun interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 957*4882a593Smuzhiyun <1 IRQ_TYPE_NONE>; /* termcount */ 958*4882a593Smuzhiyun rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ 959*4882a593Smuzhiyun ti,nand-xfer-type = "prefetch-dma"; 960*4882a593Smuzhiyun ti,nand-ecc-opt = "bch16"; 961*4882a593Smuzhiyun ti,elm-id = <&elm>; 962*4882a593Smuzhiyun nand-bus-width = <8>; 963*4882a593Smuzhiyun gpmc,device-width = <1>; 964*4882a593Smuzhiyun gpmc,sync-clk-ps = <0>; 965*4882a593Smuzhiyun gpmc,cs-on-ns = <0>; 966*4882a593Smuzhiyun gpmc,cs-rd-off-ns = <40>; 967*4882a593Smuzhiyun gpmc,cs-wr-off-ns = <40>; 968*4882a593Smuzhiyun gpmc,adv-on-ns = <0>; 969*4882a593Smuzhiyun gpmc,adv-rd-off-ns = <25>; 970*4882a593Smuzhiyun gpmc,adv-wr-off-ns = <25>; 971*4882a593Smuzhiyun gpmc,we-on-ns = <0>; 972*4882a593Smuzhiyun gpmc,we-off-ns = <20>; 973*4882a593Smuzhiyun gpmc,oe-on-ns = <3>; 974*4882a593Smuzhiyun gpmc,oe-off-ns = <30>; 975*4882a593Smuzhiyun gpmc,access-ns = <30>; 976*4882a593Smuzhiyun gpmc,rd-cycle-ns = <40>; 977*4882a593Smuzhiyun gpmc,wr-cycle-ns = <40>; 978*4882a593Smuzhiyun gpmc,bus-turnaround-ns = <0>; 979*4882a593Smuzhiyun gpmc,cycle2cycle-delay-ns = <0>; 980*4882a593Smuzhiyun gpmc,clk-activation-ns = <0>; 981*4882a593Smuzhiyun gpmc,wr-access-ns = <40>; 982*4882a593Smuzhiyun gpmc,wr-data-mux-bus-ns = <0>; 983*4882a593Smuzhiyun /* MTD partition table */ 984*4882a593Smuzhiyun /* All SPL-* partitions are sized to minimal length 985*4882a593Smuzhiyun * which can be independently programmable. For 986*4882a593Smuzhiyun * NAND flash this is equal to size of erase-block */ 987*4882a593Smuzhiyun #address-cells = <1>; 988*4882a593Smuzhiyun #size-cells = <1>; 989*4882a593Smuzhiyun partition@0 { 990*4882a593Smuzhiyun label = "NAND.SPL"; 991*4882a593Smuzhiyun reg = <0x00000000 0x00040000>; 992*4882a593Smuzhiyun }; 993*4882a593Smuzhiyun partition@1 { 994*4882a593Smuzhiyun label = "NAND.SPL.backup1"; 995*4882a593Smuzhiyun reg = <0x00040000 0x00040000>; 996*4882a593Smuzhiyun }; 997*4882a593Smuzhiyun partition@2 { 998*4882a593Smuzhiyun label = "NAND.SPL.backup2"; 999*4882a593Smuzhiyun reg = <0x00080000 0x00040000>; 1000*4882a593Smuzhiyun }; 1001*4882a593Smuzhiyun partition@3 { 1002*4882a593Smuzhiyun label = "NAND.SPL.backup3"; 1003*4882a593Smuzhiyun reg = <0x000c0000 0x00040000>; 1004*4882a593Smuzhiyun }; 1005*4882a593Smuzhiyun partition@4 { 1006*4882a593Smuzhiyun label = "NAND.u-boot-spl-os"; 1007*4882a593Smuzhiyun reg = <0x00100000 0x00080000>; 1008*4882a593Smuzhiyun }; 1009*4882a593Smuzhiyun partition@5 { 1010*4882a593Smuzhiyun label = "NAND.u-boot"; 1011*4882a593Smuzhiyun reg = <0x00180000 0x00100000>; 1012*4882a593Smuzhiyun }; 1013*4882a593Smuzhiyun partition@6 { 1014*4882a593Smuzhiyun label = "NAND.u-boot-env"; 1015*4882a593Smuzhiyun reg = <0x00280000 0x00040000>; 1016*4882a593Smuzhiyun }; 1017*4882a593Smuzhiyun partition@7 { 1018*4882a593Smuzhiyun label = "NAND.u-boot-env.backup1"; 1019*4882a593Smuzhiyun reg = <0x002c0000 0x00040000>; 1020*4882a593Smuzhiyun }; 1021*4882a593Smuzhiyun partition@8 { 1022*4882a593Smuzhiyun label = "NAND.kernel"; 1023*4882a593Smuzhiyun reg = <0x00300000 0x00700000>; 1024*4882a593Smuzhiyun }; 1025*4882a593Smuzhiyun partition@9 { 1026*4882a593Smuzhiyun label = "NAND.file-system"; 1027*4882a593Smuzhiyun reg = <0x00a00000 0x1f600000>; 1028*4882a593Smuzhiyun }; 1029*4882a593Smuzhiyun }; 1030*4882a593Smuzhiyun}; 1031*4882a593Smuzhiyun 1032*4882a593Smuzhiyun&dss { 1033*4882a593Smuzhiyun status = "okay"; 1034*4882a593Smuzhiyun 1035*4882a593Smuzhiyun pinctrl-names = "default"; 1036*4882a593Smuzhiyun pinctrl-0 = <&dss_pins>; 1037*4882a593Smuzhiyun 1038*4882a593Smuzhiyun port { 1039*4882a593Smuzhiyun dpi_out: endpoint { 1040*4882a593Smuzhiyun remote-endpoint = <&lcd_in>; 1041*4882a593Smuzhiyun data-lines = <24>; 1042*4882a593Smuzhiyun }; 1043*4882a593Smuzhiyun }; 1044*4882a593Smuzhiyun}; 1045*4882a593Smuzhiyun 1046*4882a593Smuzhiyun&dcan0 { 1047*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 1048*4882a593Smuzhiyun pinctrl-0 = <&dcan0_default>; 1049*4882a593Smuzhiyun pinctrl-1 = <&dcan0_sleep>; 1050*4882a593Smuzhiyun status = "okay"; 1051*4882a593Smuzhiyun}; 1052*4882a593Smuzhiyun 1053*4882a593Smuzhiyun&dcan1 { 1054*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 1055*4882a593Smuzhiyun pinctrl-0 = <&dcan1_default>; 1056*4882a593Smuzhiyun pinctrl-1 = <&dcan1_sleep>; 1057*4882a593Smuzhiyun status = "okay"; 1058*4882a593Smuzhiyun}; 1059*4882a593Smuzhiyun 1060*4882a593Smuzhiyun&vpfe0 { 1061*4882a593Smuzhiyun status = "okay"; 1062*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 1063*4882a593Smuzhiyun pinctrl-0 = <&vpfe0_pins_default>; 1064*4882a593Smuzhiyun pinctrl-1 = <&vpfe0_pins_sleep>; 1065*4882a593Smuzhiyun 1066*4882a593Smuzhiyun port { 1067*4882a593Smuzhiyun vpfe0_ep: endpoint { 1068*4882a593Smuzhiyun remote-endpoint = <&ov2659_1>; 1069*4882a593Smuzhiyun ti,am437x-vpfe-interface = <0>; 1070*4882a593Smuzhiyun bus-width = <8>; 1071*4882a593Smuzhiyun hsync-active = <0>; 1072*4882a593Smuzhiyun vsync-active = <0>; 1073*4882a593Smuzhiyun }; 1074*4882a593Smuzhiyun }; 1075*4882a593Smuzhiyun}; 1076*4882a593Smuzhiyun 1077*4882a593Smuzhiyun&vpfe1 { 1078*4882a593Smuzhiyun status = "okay"; 1079*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 1080*4882a593Smuzhiyun pinctrl-0 = <&vpfe1_pins_default>; 1081*4882a593Smuzhiyun pinctrl-1 = <&vpfe1_pins_sleep>; 1082*4882a593Smuzhiyun 1083*4882a593Smuzhiyun port { 1084*4882a593Smuzhiyun vpfe1_ep: endpoint { 1085*4882a593Smuzhiyun remote-endpoint = <&ov2659_0>; 1086*4882a593Smuzhiyun ti,am437x-vpfe-interface = <0>; 1087*4882a593Smuzhiyun bus-width = <8>; 1088*4882a593Smuzhiyun hsync-active = <0>; 1089*4882a593Smuzhiyun vsync-active = <0>; 1090*4882a593Smuzhiyun }; 1091*4882a593Smuzhiyun }; 1092*4882a593Smuzhiyun}; 1093*4882a593Smuzhiyun 1094*4882a593Smuzhiyun&mcasp1 { 1095*4882a593Smuzhiyun #sound-dai-cells = <0>; 1096*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 1097*4882a593Smuzhiyun pinctrl-0 = <&mcasp1_pins>; 1098*4882a593Smuzhiyun pinctrl-1 = <&mcasp1_sleep_pins>; 1099*4882a593Smuzhiyun 1100*4882a593Smuzhiyun status = "okay"; 1101*4882a593Smuzhiyun 1102*4882a593Smuzhiyun op-mode = <0>; /* MCASP_IIS_MODE */ 1103*4882a593Smuzhiyun tdm-slots = <2>; 1104*4882a593Smuzhiyun /* 4 serializers */ 1105*4882a593Smuzhiyun serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 1106*4882a593Smuzhiyun 0 0 1 2 1107*4882a593Smuzhiyun >; 1108*4882a593Smuzhiyun tx-num-evt = <32>; 1109*4882a593Smuzhiyun rx-num-evt = <32>; 1110*4882a593Smuzhiyun}; 1111*4882a593Smuzhiyun 1112*4882a593Smuzhiyun&rtc { 1113*4882a593Smuzhiyun clocks = <&clk_32k_rtc>, <&clk_32768_ck>; 1114*4882a593Smuzhiyun clock-names = "ext-clk", "int-clk"; 1115*4882a593Smuzhiyun status = "okay"; 1116*4882a593Smuzhiyun}; 1117*4882a593Smuzhiyun 1118*4882a593Smuzhiyun&cpu { 1119*4882a593Smuzhiyun cpu0-supply = <&dcdc2>; 1120*4882a593Smuzhiyun}; 1121