1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Device Tree Source for am3517 SoC 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public License 7*4882a593Smuzhiyun * version 2. This program is licensed "as is" without any warranty of any 8*4882a593Smuzhiyun * kind, whether express or implied. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun#include "omap3.dtsi" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/* AM3517 doesn't appear to have the crypto engines defined in omap3.dtsi */ 14*4882a593Smuzhiyun/delete-node/ &aes1_target; 15*4882a593Smuzhiyun/delete-node/ &aes2_target; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun/ { 18*4882a593Smuzhiyun aliases { 19*4882a593Smuzhiyun serial3 = &uart4; 20*4882a593Smuzhiyun can = &hecc; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun cpus { 24*4882a593Smuzhiyun cpu: cpu@0 { 25*4882a593Smuzhiyun /* Based on OMAP3630 variants OPP50 and OPP100 */ 26*4882a593Smuzhiyun operating-points-v2 = <&cpu0_opp_table>; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun clock-latency = <300000>; /* From legacy driver */ 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun cpu0_opp_table: opp-table { 33*4882a593Smuzhiyun compatible = "operating-points-v2-ti-cpu"; 34*4882a593Smuzhiyun syscon = <&scm_conf>; 35*4882a593Smuzhiyun /* 36*4882a593Smuzhiyun * AM3517 TRM only lists 600MHz @ 1.2V, but omap36xx 37*4882a593Smuzhiyun * appear to operate at 300MHz as well. Since AM3517 only 38*4882a593Smuzhiyun * lists one operating voltage, it will remain fixed at 1.2V 39*4882a593Smuzhiyun */ 40*4882a593Smuzhiyun opp50-300000000 { 41*4882a593Smuzhiyun opp-hz = /bits/ 64 <300000000>; 42*4882a593Smuzhiyun opp-microvolt = <1200000>; 43*4882a593Smuzhiyun opp-supported-hw = <0xffffffff 0xffffffff>; 44*4882a593Smuzhiyun opp-suspend; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun opp100-600000000 { 48*4882a593Smuzhiyun opp-hz = /bits/ 64 <600000000>; 49*4882a593Smuzhiyun opp-microvolt = <1200000>; 50*4882a593Smuzhiyun opp-supported-hw = <0xffffffff 0xffffffff>; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun ocp@68000000 { 55*4882a593Smuzhiyun am35x_otg_hs: am35x_otg_hs@5c040000 { 56*4882a593Smuzhiyun compatible = "ti,omap3-musb"; 57*4882a593Smuzhiyun ti,hwmods = "am35x_otg_hs"; 58*4882a593Smuzhiyun status = "disabled"; 59*4882a593Smuzhiyun reg = <0x5c040000 0x1000>; 60*4882a593Smuzhiyun interrupts = <71>; 61*4882a593Smuzhiyun interrupt-names = "mc"; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun davinci_emac: ethernet@5c000000 { 65*4882a593Smuzhiyun compatible = "ti,am3517-emac"; 66*4882a593Smuzhiyun ti,hwmods = "davinci_emac"; 67*4882a593Smuzhiyun status = "disabled"; 68*4882a593Smuzhiyun reg = <0x5c000000 0x30000>; 69*4882a593Smuzhiyun interrupts = <67 68 69 70>; 70*4882a593Smuzhiyun syscon = <&scm_conf>; 71*4882a593Smuzhiyun ti,davinci-ctrl-reg-offset = <0x10000>; 72*4882a593Smuzhiyun ti,davinci-ctrl-mod-reg-offset = <0>; 73*4882a593Smuzhiyun ti,davinci-ctrl-ram-offset = <0x20000>; 74*4882a593Smuzhiyun ti,davinci-ctrl-ram-size = <0x2000>; 75*4882a593Smuzhiyun ti,davinci-rmii-en = /bits/ 8 <1>; 76*4882a593Smuzhiyun local-mac-address = [ 00 00 00 00 00 00 ]; 77*4882a593Smuzhiyun clocks = <&emac_ick>; 78*4882a593Smuzhiyun clock-names = "ick"; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun davinci_mdio: mdio@5c030000 { 82*4882a593Smuzhiyun compatible = "ti,davinci_mdio"; 83*4882a593Smuzhiyun ti,hwmods = "davinci_mdio"; 84*4882a593Smuzhiyun status = "disabled"; 85*4882a593Smuzhiyun reg = <0x5c030000 0x1000>; 86*4882a593Smuzhiyun bus_freq = <1000000>; 87*4882a593Smuzhiyun #address-cells = <1>; 88*4882a593Smuzhiyun #size-cells = <0>; 89*4882a593Smuzhiyun clocks = <&emac_fck>; 90*4882a593Smuzhiyun clock-names = "fck"; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun uart4: serial@4809e000 { 94*4882a593Smuzhiyun compatible = "ti,omap3-uart"; 95*4882a593Smuzhiyun ti,hwmods = "uart4"; 96*4882a593Smuzhiyun status = "disabled"; 97*4882a593Smuzhiyun reg = <0x4809e000 0x400>; 98*4882a593Smuzhiyun interrupts = <84>; 99*4882a593Smuzhiyun dmas = <&sdma 55 &sdma 54>; 100*4882a593Smuzhiyun dma-names = "tx", "rx"; 101*4882a593Smuzhiyun clock-frequency = <48000000>; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun omap3_pmx_core2: pinmux@480025d8 { 105*4882a593Smuzhiyun compatible = "ti,omap3-padconf", "pinctrl-single"; 106*4882a593Smuzhiyun reg = <0x480025d8 0x24>; 107*4882a593Smuzhiyun #address-cells = <1>; 108*4882a593Smuzhiyun #size-cells = <0>; 109*4882a593Smuzhiyun #pinctrl-cells = <1>; 110*4882a593Smuzhiyun #interrupt-cells = <1>; 111*4882a593Smuzhiyun interrupt-controller; 112*4882a593Smuzhiyun pinctrl-single,register-width = <16>; 113*4882a593Smuzhiyun pinctrl-single,function-mask = <0xff1f>; 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun hecc: can@5c050000 { 117*4882a593Smuzhiyun compatible = "ti,am3517-hecc"; 118*4882a593Smuzhiyun status = "disabled"; 119*4882a593Smuzhiyun reg = <0x5c050000 0x80>, 120*4882a593Smuzhiyun <0x5c053000 0x180>, 121*4882a593Smuzhiyun <0x5c052000 0x200>; 122*4882a593Smuzhiyun reg-names = "hecc", "hecc-ram", "mbx"; 123*4882a593Smuzhiyun interrupts = <24>; 124*4882a593Smuzhiyun clocks = <&hecc_ck>; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun /* 128*4882a593Smuzhiyun * On am3517 the OCP registers do not seem to be accessible 129*4882a593Smuzhiyun * similar to the omap34xx. Maybe SGX is permanently set to 130*4882a593Smuzhiyun * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is 131*4882a593Smuzhiyun * write-only at 0x50000e10. We detect SGX based on the SGX 132*4882a593Smuzhiyun * revision register instead of the unreadable OCP revision 133*4882a593Smuzhiyun * register. 134*4882a593Smuzhiyun */ 135*4882a593Smuzhiyun sgx_module: target-module@50000000 { 136*4882a593Smuzhiyun compatible = "ti,sysc-omap2", "ti,sysc"; 137*4882a593Smuzhiyun reg = <0x50000014 0x4>; 138*4882a593Smuzhiyun reg-names = "rev"; 139*4882a593Smuzhiyun clocks = <&sgx_fck>, <&sgx_ick>; 140*4882a593Smuzhiyun clock-names = "fck", "ick"; 141*4882a593Smuzhiyun #address-cells = <1>; 142*4882a593Smuzhiyun #size-cells = <1>; 143*4882a593Smuzhiyun ranges = <0 0x50000000 0x4000>; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun /* 146*4882a593Smuzhiyun * Closed source PowerVR driver, no child device 147*4882a593Smuzhiyun * binding or driver in mainline 148*4882a593Smuzhiyun */ 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun }; 151*4882a593Smuzhiyun}; 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun/* Not currently working, probably needs at least different clocks */ 154*4882a593Smuzhiyun&rng_target { 155*4882a593Smuzhiyun status = "disabled"; 156*4882a593Smuzhiyun /delete-property/ clocks; 157*4882a593Smuzhiyun}; 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun/* Table Table 5-79 of the TRM shows 480ab000 is reserved */ 160*4882a593Smuzhiyun&usb_otg_hs { 161*4882a593Smuzhiyun status = "disabled"; 162*4882a593Smuzhiyun}; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun&iva { 165*4882a593Smuzhiyun status = "disabled"; 166*4882a593Smuzhiyun}; 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun&mailbox { 169*4882a593Smuzhiyun status = "disabled"; 170*4882a593Smuzhiyun}; 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun&mmu_isp { 173*4882a593Smuzhiyun status = "disabled"; 174*4882a593Smuzhiyun}; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun#include "am35xx-clocks.dtsi" 177*4882a593Smuzhiyun#include "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun/* Preferred always-on timer for clocksource */ 180*4882a593Smuzhiyun&timer1_target { 181*4882a593Smuzhiyun ti,no-reset-on-init; 182*4882a593Smuzhiyun ti,no-idle; 183*4882a593Smuzhiyun timer@0 { 184*4882a593Smuzhiyun assigned-clocks = <&gpt1_fck>; 185*4882a593Smuzhiyun assigned-clock-parents = <&sys_ck>; 186*4882a593Smuzhiyun }; 187*4882a593Smuzhiyun}; 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun/* Preferred timer for clockevent */ 190*4882a593Smuzhiyun&timer2_target { 191*4882a593Smuzhiyun ti,no-reset-on-init; 192*4882a593Smuzhiyun ti,no-idle; 193*4882a593Smuzhiyun timer@0 { 194*4882a593Smuzhiyun assigned-clocks = <&gpt2_fck>; 195*4882a593Smuzhiyun assigned-clock-parents = <&sys_ck>; 196*4882a593Smuzhiyun }; 197*4882a593Smuzhiyun}; 198