xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/am3517-som.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (C) 2016 Derald D. Woods <woods.technical@gmail.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Based on am3517-evm.dts
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun/ {
9*4882a593Smuzhiyun	cpus {
10*4882a593Smuzhiyun		cpu@0 {
11*4882a593Smuzhiyun			cpu0-supply = <&vdd_core_reg>;
12*4882a593Smuzhiyun		};
13*4882a593Smuzhiyun	};
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun	wl12xx_buffer: wl12xx_buf {
16*4882a593Smuzhiyun		compatible = "regulator-fixed";
17*4882a593Smuzhiyun		regulator-name = "wl1271_buf";
18*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
19*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
20*4882a593Smuzhiyun		pinctrl-names = "default";
21*4882a593Smuzhiyun		pinctrl-0 = <&wl12xx_buffer_pins>;
22*4882a593Smuzhiyun		gpio = <&gpio5 1 GPIO_ACTIVE_LOW>; /* gpio 129 */
23*4882a593Smuzhiyun		regulator-always-on;
24*4882a593Smuzhiyun		vin-supply = <&vdd_1v8_reg>;
25*4882a593Smuzhiyun	};
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun	wl12xx_vmmc2: wl12xx_vmmc2 {
28*4882a593Smuzhiyun		compatible = "regulator-fixed";
29*4882a593Smuzhiyun		regulator-name = "vwl1271";
30*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
31*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
32*4882a593Smuzhiyun		pinctrl-names = "default";
33*4882a593Smuzhiyun		pinctrl-0 = <&wl12xx_wkup_pins>;
34*4882a593Smuzhiyun		gpio = <&gpio1 3 GPIO_ACTIVE_HIGH >; /* gpio 3 */
35*4882a593Smuzhiyun		startup-delay-us = <70000>;
36*4882a593Smuzhiyun		enable-active-high;
37*4882a593Smuzhiyun		regulator-always-on;
38*4882a593Smuzhiyun		vin-supply = <&wl12xx_buffer>;
39*4882a593Smuzhiyun	};
40*4882a593Smuzhiyun};
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun&gpmc {
43*4882a593Smuzhiyun	ranges = <0 0 0x30000000 0x1000000>;	/* CS0: 16MB for NAND */
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun	nand@0,0 {
46*4882a593Smuzhiyun		compatible = "ti,omap2-nand";
47*4882a593Smuzhiyun		linux,mtd-name = "micron,mt29f4g16abchch";
48*4882a593Smuzhiyun		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
49*4882a593Smuzhiyun		nand-bus-width = <16>;
50*4882a593Smuzhiyun		ti,nand-ecc-opt = "bch8";
51*4882a593Smuzhiyun		gpmc,sync-clk-ps = <0>;
52*4882a593Smuzhiyun		gpmc,cs-on-ns = <0>;
53*4882a593Smuzhiyun		gpmc,cs-rd-off-ns = <44>;
54*4882a593Smuzhiyun		gpmc,cs-wr-off-ns = <44>;
55*4882a593Smuzhiyun		gpmc,adv-on-ns = <6>;
56*4882a593Smuzhiyun		gpmc,adv-rd-off-ns = <34>;
57*4882a593Smuzhiyun		gpmc,adv-wr-off-ns = <44>;
58*4882a593Smuzhiyun		gpmc,we-off-ns = <40>;
59*4882a593Smuzhiyun		gpmc,oe-off-ns = <54>;
60*4882a593Smuzhiyun		gpmc,access-ns = <64>;
61*4882a593Smuzhiyun		gpmc,rd-cycle-ns = <82>;
62*4882a593Smuzhiyun		gpmc,wr-cycle-ns = <82>;
63*4882a593Smuzhiyun		gpmc,wr-access-ns = <40>;
64*4882a593Smuzhiyun		gpmc,wr-data-mux-bus-ns = <0>;
65*4882a593Smuzhiyun		gpmc,device-width = <2>;
66*4882a593Smuzhiyun		#address-cells = <1>;
67*4882a593Smuzhiyun		#size-cells = <1>;
68*4882a593Smuzhiyun	};
69*4882a593Smuzhiyun};
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun&i2c1 {
72*4882a593Smuzhiyun	pinctrl-names = "default";
73*4882a593Smuzhiyun	pinctrl-0 = <&i2c1_pins>;
74*4882a593Smuzhiyun	clock-frequency = <400000>;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun	s35390a: s35390a@30 {
77*4882a593Smuzhiyun		compatible = "sii,s35390a";
78*4882a593Smuzhiyun		reg = <0x30>;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun		pinctrl-names = "default";
81*4882a593Smuzhiyun		pinctrl-0 = <&rtc_pins>;
82*4882a593Smuzhiyun		interrupts-extended = <&gpio2 23 IRQ_TYPE_EDGE_FALLING>; /* gpio_55 */
83*4882a593Smuzhiyun	};
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun	tps: tps65023@48 {
86*4882a593Smuzhiyun		compatible = "ti,tps65023";
87*4882a593Smuzhiyun		reg = <0x48>;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun		regulators {
90*4882a593Smuzhiyun			vdd_core_reg: VDCDC1 {
91*4882a593Smuzhiyun				regulator-name = "vdd_core";
92*4882a593Smuzhiyun				regulator-always-on;
93*4882a593Smuzhiyun				regulator-min-microvolt = <1200000>;
94*4882a593Smuzhiyun				regulator-max-microvolt = <1200000>;
95*4882a593Smuzhiyun			};
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun			vdd_io_reg: VDCDC2 {
98*4882a593Smuzhiyun				regulator-name = "vdd_io";
99*4882a593Smuzhiyun				regulator-always-on;
100*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
101*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
102*4882a593Smuzhiyun			};
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun			vdd_1v8_reg: VDCDC3 {
105*4882a593Smuzhiyun				regulator-name = "vdd_1v8";
106*4882a593Smuzhiyun				regulator-always-on;
107*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
108*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
109*4882a593Smuzhiyun			};
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun			vdd_usb18_reg: LDO1 {
112*4882a593Smuzhiyun				regulator-name = "vdd_usb18";
113*4882a593Smuzhiyun				regulator-always-on;
114*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
115*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
116*4882a593Smuzhiyun			};
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun			vdd_usb33_reg: LDO2 {
119*4882a593Smuzhiyun				regulator-name = "vdd_usb33";
120*4882a593Smuzhiyun				regulator-always-on;
121*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
122*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
123*4882a593Smuzhiyun			};
124*4882a593Smuzhiyun		};
125*4882a593Smuzhiyun	};
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun	touchscreen: tsc2004@4b {
128*4882a593Smuzhiyun		compatible = "ti,tsc2004";
129*4882a593Smuzhiyun		reg = <0x4b>;
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun		vio-supply = <&vdd_io_reg>;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun		pinctrl-names = "default";
134*4882a593Smuzhiyun		pinctrl-0 = <&tsc2004_pins>;
135*4882a593Smuzhiyun		interrupts-extended = <&gpio3 1 IRQ_TYPE_EDGE_RISING>; /* gpio_65 */
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun		touchscreen-fuzz-x = <4>;
138*4882a593Smuzhiyun		touchscreen-fuzz-y = <7>;
139*4882a593Smuzhiyun		touchscreen-fuzz-pressure = <2>;
140*4882a593Smuzhiyun		touchscreen-size-x = <480>;
141*4882a593Smuzhiyun		touchscreen-size-y = <272>;
142*4882a593Smuzhiyun		touchscreen-max-pressure = <2048>;
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun		ti,x-plate-ohms = <280>;
145*4882a593Smuzhiyun		ti,esd-recovery-timeout-ms = <8000>;
146*4882a593Smuzhiyun	};
147*4882a593Smuzhiyun};
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun&mmc2 {
150*4882a593Smuzhiyun	interrupts-extended = <&intc 86 /* &omap3_pmx_core 0x12c */>;
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun	status = "okay";
153*4882a593Smuzhiyun	pinctrl-names = "default";
154*4882a593Smuzhiyun	pinctrl-0 = <&mmc2_pins>;
155*4882a593Smuzhiyun	vmmc-supply = <&wl12xx_vmmc2>;
156*4882a593Smuzhiyun	non-removable;
157*4882a593Smuzhiyun	bus-width = <4>;
158*4882a593Smuzhiyun	cap-power-off-card;
159*4882a593Smuzhiyun	#address-cells = <1>;
160*4882a593Smuzhiyun	#size-cells = <0>;
161*4882a593Smuzhiyun	wlcore: wlcore@2 {
162*4882a593Smuzhiyun		compatible = "ti,wl1271";
163*4882a593Smuzhiyun		reg = <2>;
164*4882a593Smuzhiyun		interrupt-parent = <&gpio6>;
165*4882a593Smuzhiyun		interrupts = <10 IRQ_TYPE_EDGE_RISING>; /* gpio_170 */
166*4882a593Smuzhiyun		ref-clock-frequency = <26000000>;
167*4882a593Smuzhiyun		tcxo-clock-frequency = <26000000>;
168*4882a593Smuzhiyun	};
169*4882a593Smuzhiyun};
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun&uart2 {
172*4882a593Smuzhiyun	pinctrl-names = "default";
173*4882a593Smuzhiyun	pinctrl-0 = <&uart2_pins>;
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun	bluetooth {
176*4882a593Smuzhiyun		compatible = "ti,wl1271-st";
177*4882a593Smuzhiyun		enable-gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; /* gpio 56 */
178*4882a593Smuzhiyun		max-speed = <3000000>;
179*4882a593Smuzhiyun	};
180*4882a593Smuzhiyun};
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun&omap3_pmx_core {
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun	i2c1_pins: pinmux_i2c1_pins {
185*4882a593Smuzhiyun		pinctrl-single,pins = <
186*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT_PULLUP | MUX_MODE0)  /* i2c1_scl */
187*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT_PULLUP | MUX_MODE0)  /* i2c1_sda */
188*4882a593Smuzhiyun		>;
189*4882a593Smuzhiyun	};
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun	wl12xx_buffer_pins: pinmux_wl12xx_buffer_pins {
192*4882a593Smuzhiyun		pinctrl-single,pins = <
193*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2156, PIN_OUTPUT | MUX_MODE4)  /* mmc1_dat7.gpio_129 */
194*4882a593Smuzhiyun		>;
195*4882a593Smuzhiyun	};
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun	mmc2_pins: pinmux_mmc2_pins {
198*4882a593Smuzhiyun		pinctrl-single,pins = <
199*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0)  /* mmc2_clk.mmc2_clk */
200*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0)  /* mmc2_cmd.mmc2_cmd */
201*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0)  /* mmc2_dat0.mmc2_dat0 */
202*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0)  /* mmc2_dat1.mmc2_dat1 */
203*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0)  /* mmc2_dat2.mmc2_dat2 */
204*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0)  /* mmc2_dat3.mmc2_dat3 */
205*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2164, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat4.mmc2_dir_dat0 */
206*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat5.mmc2_dir_dat1 */
207*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE1) /* mmc2_dat6.mmc2_dir_cmd */
208*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x216a, PIN_INPUT | MUX_MODE1) /* mmc2_dat7.mmc2_clkin */
209*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE4)	/* hdq_sio.gpio_170 */
210*4882a593Smuzhiyun		>;
211*4882a593Smuzhiyun	};
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun	rtc_pins: pinmux_rtc_pins {
214*4882a593Smuzhiyun		pinctrl-single,pins = <
215*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x20b6, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_ncs4.gpio_55 */
216*4882a593Smuzhiyun		>;
217*4882a593Smuzhiyun	};
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun	tsc2004_pins: pinmux_tsc2004_pins {
220*4882a593Smuzhiyun		pinctrl-single,pins = <
221*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT | MUX_MODE4) /* gpmc_wait3.gpio_65 */
222*4882a593Smuzhiyun		>;
223*4882a593Smuzhiyun	};
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun	uart2_pins: pinmux_uart2_pins {
226*4882a593Smuzhiyun		pinctrl-single,pins = <
227*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT_PULLUP | MUX_MODE0)		/* uart2_cts */
228*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT_PULLUP | MUX_MODE0)	/* uart2_rts */
229*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0)		/* uart2_tx */
230*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0)		/* uart2_rx */
231*4882a593Smuzhiyun			OMAP3_CORE1_IOPAD(0x20b8, PIN_INPUT | MUX_MODE0)		/* gpio_56 */
232*4882a593Smuzhiyun		>;
233*4882a593Smuzhiyun	};
234*4882a593Smuzhiyun};
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun&omap3_pmx_wkup {
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun	wl12xx_wkup_pins: pinmux_wl12xx_wkup_pins {
239*4882a593Smuzhiyun		pinctrl-single,pins = <
240*4882a593Smuzhiyun			OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4)	/* sys_boot1.gpio_3 */
241*4882a593Smuzhiyun		>;
242*4882a593Smuzhiyun	};
243*4882a593Smuzhiyun};
244