xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/am335x-sl50.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (C) 2015 Toby Churchill - http://www.toby-churchill.com/
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun/dts-v1/;
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun#include "am33xx.dtsi"
8*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h>
9*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun/ {
12*4882a593Smuzhiyun	model = "Toby Churchill SL50 Series";
13*4882a593Smuzhiyun	compatible = "tcl,am335x-sl50", "ti,am33xx";
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun	cpus {
16*4882a593Smuzhiyun		cpu@0 {
17*4882a593Smuzhiyun			cpu0-supply = <&dcdc2_reg>;
18*4882a593Smuzhiyun		};
19*4882a593Smuzhiyun	};
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun	memory@80000000 {
22*4882a593Smuzhiyun		device_type = "memory";
23*4882a593Smuzhiyun		reg = <0x80000000 0x20000000>; /* 512 MB */
24*4882a593Smuzhiyun	};
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun	chosen {
27*4882a593Smuzhiyun		stdout-path = &uart0;
28*4882a593Smuzhiyun	};
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun	leds {
31*4882a593Smuzhiyun		compatible = "gpio-leds";
32*4882a593Smuzhiyun		pinctrl-names = "default";
33*4882a593Smuzhiyun		pinctrl-0 = <&led_pins>;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun		led0 {
36*4882a593Smuzhiyun			label = "sl50:red:usr0";
37*4882a593Smuzhiyun			gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
38*4882a593Smuzhiyun			default-state = "off";
39*4882a593Smuzhiyun		};
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun		led1 {
42*4882a593Smuzhiyun			label = "sl50:green:usr1";
43*4882a593Smuzhiyun			gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
44*4882a593Smuzhiyun			default-state = "off";
45*4882a593Smuzhiyun		};
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun		led2 {
48*4882a593Smuzhiyun			label = "sl50:red:usr2";
49*4882a593Smuzhiyun			gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
50*4882a593Smuzhiyun			default-state = "off";
51*4882a593Smuzhiyun		};
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun		led3 {
54*4882a593Smuzhiyun			label = "sl50:green:usr3";
55*4882a593Smuzhiyun			gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
56*4882a593Smuzhiyun			default-state = "off";
57*4882a593Smuzhiyun		};
58*4882a593Smuzhiyun	};
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun	backlight0: disp0 {
61*4882a593Smuzhiyun		compatible = "pwm-backlight";
62*4882a593Smuzhiyun		pinctrl-names = "default";
63*4882a593Smuzhiyun		pinctrl-0 = <&backlight0_pins>;
64*4882a593Smuzhiyun		pwms = <&ehrpwm1 0 500000 PWM_POLARITY_INVERTED>;
65*4882a593Smuzhiyun		brightness-levels = < 0  1  2  3  4  5  6  7  8  9
66*4882a593Smuzhiyun				     10 11 12 13 14 15 16 17 18 19
67*4882a593Smuzhiyun				     20 21 22 23 24 25 26 27 28 29
68*4882a593Smuzhiyun				     30 31 32 33 34 35 36 37 38 39
69*4882a593Smuzhiyun				     40 41 42 43 44 45 46 47 48 49
70*4882a593Smuzhiyun				     50 51 52 53 54 55 56 57 58 59
71*4882a593Smuzhiyun				     60 61 62 63 64 65 66 67 68 69
72*4882a593Smuzhiyun				     70 71 72 73 74 75 76 77 78 79
73*4882a593Smuzhiyun				     80 81 82 83 84 85 86 87 88 89
74*4882a593Smuzhiyun				     90 91 92 93 94 95 96 97 98 99
75*4882a593Smuzhiyun				    100>;
76*4882a593Smuzhiyun		default-brightness-level = <50>;
77*4882a593Smuzhiyun		enable-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
78*4882a593Smuzhiyun		power-supply = <&vdd_sys_reg>;
79*4882a593Smuzhiyun	};
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun	backlight1: disp1 {
82*4882a593Smuzhiyun		compatible = "pwm-backlight";
83*4882a593Smuzhiyun		pinctrl-names = "default";
84*4882a593Smuzhiyun		pinctrl-0 = <&backlight1_pins>;
85*4882a593Smuzhiyun		pwms = <&ehrpwm1 1 500000 PWM_POLARITY_INVERTED>;
86*4882a593Smuzhiyun		brightness-levels = < 0  1  2  3  4  5  6  7  8  9
87*4882a593Smuzhiyun				     10 11 12 13 14 15 16 17 18 19
88*4882a593Smuzhiyun				     20 21 22 23 24 25 26 27 28 29
89*4882a593Smuzhiyun				     30 31 32 33 34 35 36 37 38 39
90*4882a593Smuzhiyun				     40 41 42 43 44 45 46 47 48 49
91*4882a593Smuzhiyun				     50 51 52 53 54 55 56 57 58 59
92*4882a593Smuzhiyun				     60 61 62 63 64 65 66 67 68 69
93*4882a593Smuzhiyun				     70 71 72 73 74 75 76 77 78 79
94*4882a593Smuzhiyun				     80 81 82 83 84 85 86 87 88 89
95*4882a593Smuzhiyun				     90 91 92 93 94 95 96 97 98 99
96*4882a593Smuzhiyun				    100>;
97*4882a593Smuzhiyun		default-brightness-level = <50>;
98*4882a593Smuzhiyun		enable-gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
99*4882a593Smuzhiyun		power-supply = <&vdd_sys_reg>;
100*4882a593Smuzhiyun	};
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun	clocks {
103*4882a593Smuzhiyun		compatible = "simple-bus";
104*4882a593Smuzhiyun		#address-cells = <1>;
105*4882a593Smuzhiyun		#size-cells = <0>;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun		/* audio external oscillator */
108*4882a593Smuzhiyun		audio_mclk_fixed: oscillator@0 {
109*4882a593Smuzhiyun			compatible = "fixed-clock";
110*4882a593Smuzhiyun			#clock-cells = <0>;
111*4882a593Smuzhiyun			clock-frequency  = <24576000>;	/* 24.576MHz */
112*4882a593Smuzhiyun		};
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun		audio_mclk: audio_mclk_gate@0 {
115*4882a593Smuzhiyun			compatible = "gpio-gate-clock";
116*4882a593Smuzhiyun			#clock-cells = <0>;
117*4882a593Smuzhiyun			pinctrl-names = "default";
118*4882a593Smuzhiyun			pinctrl-0 = <&audio_mclk_pins>;
119*4882a593Smuzhiyun			clocks = <&audio_mclk_fixed>;
120*4882a593Smuzhiyun			enable-gpios = <&gpio1 27 0>;
121*4882a593Smuzhiyun		};
122*4882a593Smuzhiyun	};
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun	panel: lcd_panel {
125*4882a593Smuzhiyun		compatible = "ti,tilcdc,panel";
126*4882a593Smuzhiyun		pinctrl-names = "default";
127*4882a593Smuzhiyun		pinctrl-0 = <&lcd_pins>;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun		panel-info {
130*4882a593Smuzhiyun			ac-bias = <255>;
131*4882a593Smuzhiyun			ac-bias-intrpt = <0>;
132*4882a593Smuzhiyun			dma-burst-sz = <16>;
133*4882a593Smuzhiyun			bpp = <16>;
134*4882a593Smuzhiyun			fdd = <0x80>;
135*4882a593Smuzhiyun			tft-alt-mode = <0>;
136*4882a593Smuzhiyun			mono-8bit-mode = <0>;
137*4882a593Smuzhiyun			sync-edge = <0>;
138*4882a593Smuzhiyun			sync-ctrl = <1>;
139*4882a593Smuzhiyun			raster-order = <0>;
140*4882a593Smuzhiyun			fifo-th = <0>;
141*4882a593Smuzhiyun		};
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun		display-timings {
144*4882a593Smuzhiyun			native-mode = <&timing0>;
145*4882a593Smuzhiyun			timing0: 960x128 {
146*4882a593Smuzhiyun				clock-frequency = <18000000>;
147*4882a593Smuzhiyun				hactive = <960>;
148*4882a593Smuzhiyun				vactive = <272>;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun				hback-porch = <40>;
151*4882a593Smuzhiyun				hfront-porch = <16>;
152*4882a593Smuzhiyun				hsync-len = <24>;
153*4882a593Smuzhiyun				hsync-active = <0>;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun				vback-porch = <3>;
156*4882a593Smuzhiyun				vfront-porch = <8>;
157*4882a593Smuzhiyun				vsync-len = <4>;
158*4882a593Smuzhiyun				vsync-active = <0>;
159*4882a593Smuzhiyun			};
160*4882a593Smuzhiyun		};
161*4882a593Smuzhiyun	};
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun	sound {
164*4882a593Smuzhiyun		compatible = "audio-graph-card";
165*4882a593Smuzhiyun		label = "sound-card";
166*4882a593Smuzhiyun		pinctrl-names = "default";
167*4882a593Smuzhiyun		pinctrl-0 = <&audio_pa_pins>;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun		widgets = "Headphone", "Headphone Jack",
170*4882a593Smuzhiyun			  "Speaker", "Speaker External",
171*4882a593Smuzhiyun			  "Line", "Line In",
172*4882a593Smuzhiyun			  "Microphone", "Microphone Jack";
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun		routing = "Headphone Jack",	"HPLOUT",
175*4882a593Smuzhiyun			  "Headphone Jack",	"HPROUT",
176*4882a593Smuzhiyun			  "Amplifier",		"MONO_LOUT",
177*4882a593Smuzhiyun			  "Speaker External",	"Amplifier",
178*4882a593Smuzhiyun			  "LINE1R",		"Line In",
179*4882a593Smuzhiyun			  "LINE1L",		"Line In",
180*4882a593Smuzhiyun			  "MIC3L",		"Microphone Jack",
181*4882a593Smuzhiyun			  "MIC3R",		"Microphone Jack",
182*4882a593Smuzhiyun			  "Microphone Jack",	"Mic Bias";
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun		dais = <&cpu_port>;
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun		pa-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
187*4882a593Smuzhiyun	};
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun	emmc_pwrseq: pwrseq@0 {
190*4882a593Smuzhiyun		compatible = "mmc-pwrseq-emmc";
191*4882a593Smuzhiyun		pinctrl-names = "default";
192*4882a593Smuzhiyun		pinctrl-0 = <&emmc_pwrseq_pins>;
193*4882a593Smuzhiyun		reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
194*4882a593Smuzhiyun	};
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun	vdd_sys_reg: regulator@0 {
197*4882a593Smuzhiyun		compatible = "regulator-fixed";
198*4882a593Smuzhiyun		regulator-name = "vdd_sys_reg";
199*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
200*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
201*4882a593Smuzhiyun		regulator-always-on;
202*4882a593Smuzhiyun	};
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun	vmmcsd_fixed: fixedregulator0 {
205*4882a593Smuzhiyun		compatible = "regulator-fixed";
206*4882a593Smuzhiyun		regulator-name = "vmmcsd_fixed";
207*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
208*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
209*4882a593Smuzhiyun	};
210*4882a593Smuzhiyun};
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun&am33xx_pinmux {
213*4882a593Smuzhiyun	pinctrl-names = "default";
214*4882a593Smuzhiyun	pinctrl-0 = <&lwb_pins>;
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun	audio_pins: pinmux_audio_pins {
217*4882a593Smuzhiyun		pinctrl-single,pins = <
218*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE0)
219*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0)
220*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0)
221*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0)
222*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2)
223*4882a593Smuzhiyun		>;
224*4882a593Smuzhiyun	};
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun	audio_pa_pins: pinmux_audio_pa_pins {
227*4882a593Smuzhiyun		pinctrl-single,pins = <
228*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* SoundPA_en - mcasp0_aclkr.gpio3_18 */
229*4882a593Smuzhiyun		>;
230*4882a593Smuzhiyun	};
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun	audio_mclk_pins: pinmux_audio_mclk_pins {
233*4882a593Smuzhiyun		pinctrl-single,pins = <
234*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* gpmc_a11.gpio1_27 */
235*4882a593Smuzhiyun		>;
236*4882a593Smuzhiyun	};
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun	backlight0_pins: pinmux_backlight0_pins {
239*4882a593Smuzhiyun		pinctrl-single,pins = <
240*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE7)	/* gpmc_wen.gpio2_4 */
241*4882a593Smuzhiyun		>;
242*4882a593Smuzhiyun	};
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun	backlight1_pins: pinmux_backlight1_pins {
245*4882a593Smuzhiyun		pinctrl-single,pins = <
246*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7)     /* gpmc_ad10.gpio0_26 */
247*4882a593Smuzhiyun		>;
248*4882a593Smuzhiyun	};
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun	lcd_pins: pinmux_lcd_pins {
251*4882a593Smuzhiyun		pinctrl-single,pins = <
252*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
253*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
254*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
255*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
256*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
257*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
258*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
259*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
260*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
261*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
262*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
263*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
264*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
265*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
266*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
267*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
268*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
269*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
270*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
271*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
272*4882a593Smuzhiyun		>;
273*4882a593Smuzhiyun	};
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun	led_pins: pinmux_led_pins {
276*4882a593Smuzhiyun		pinctrl-single,pins = <
277*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7)	/* gpmc_a5.gpio1_21 */
278*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7)	/* gpmc_a6.gpio1_22 */
279*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7)	/* gpmc_a7.gpio1_23 */
280*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7)	/* gpmc_a8.gpio1_24 */
281*4882a593Smuzhiyun		>;
282*4882a593Smuzhiyun	};
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun	uart0_pins: pinmux_uart0_pins {
285*4882a593Smuzhiyun		pinctrl-single,pins = <
286*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
287*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
288*4882a593Smuzhiyun		>;
289*4882a593Smuzhiyun	};
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun	uart1_pins: pinmux_uart1_pins {
292*4882a593Smuzhiyun		pinctrl-single,pins = <
293*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
294*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
295*4882a593Smuzhiyun		>;
296*4882a593Smuzhiyun	};
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun	uart4_pins: pinmux_uart4_pins {
299*4882a593Smuzhiyun		pinctrl-single,pins = <
300*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6)	/* gpmc_wait0.uart4_rxd */
301*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6)	/* gpmc_wpn.uart4_txd */
302*4882a593Smuzhiyun		>;
303*4882a593Smuzhiyun	};
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun	i2c0_pins: pinmux_i2c0_pins {
306*4882a593Smuzhiyun		pinctrl-single,pins = <
307*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
308*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
309*4882a593Smuzhiyun		>;
310*4882a593Smuzhiyun	};
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun	i2c2_pins: pinmux_i2c2_pins {
313*4882a593Smuzhiyun		pinctrl-single,pins = <
314*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3)	/* uart1_ctsn.i2c2_sda */
315*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3)	/* uart1_rtsn.i2c2_scl */
316*4882a593Smuzhiyun		>;
317*4882a593Smuzhiyun	};
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun	cpsw_default: cpsw_default {
320*4882a593Smuzhiyun		pinctrl-single,pins = <
321*4882a593Smuzhiyun			/* Slave 1 */
322*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0)
323*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
324*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE0)
325*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
326*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
327*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
328*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
329*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
330*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
331*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE0)
332*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE0)
333*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE0)
334*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE0)
335*4882a593Smuzhiyun		>;
336*4882a593Smuzhiyun	};
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun	cpsw_sleep: cpsw_sleep {
339*4882a593Smuzhiyun		pinctrl-single,pins = <
340*4882a593Smuzhiyun			/* Slave 1 reset value */
341*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
342*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
343*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
344*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
345*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
346*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
347*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
348*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
349*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
350*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
351*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
352*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
353*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
354*4882a593Smuzhiyun		>;
355*4882a593Smuzhiyun	};
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun	davinci_mdio_default: davinci_mdio_default {
358*4882a593Smuzhiyun		pinctrl-single,pins = <
359*4882a593Smuzhiyun			/* MDIO */
360*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
361*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
362*4882a593Smuzhiyun			/* Ethernet */
363*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE7)	/* Ethernet_nRST - gpmc_ad14.gpio1_14 */
364*4882a593Smuzhiyun		>;
365*4882a593Smuzhiyun	};
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun	davinci_mdio_sleep: davinci_mdio_sleep {
368*4882a593Smuzhiyun		pinctrl-single,pins = <
369*4882a593Smuzhiyun			/* MDIO reset value */
370*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
371*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
372*4882a593Smuzhiyun		>;
373*4882a593Smuzhiyun	};
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun	mmc1_pins: pinmux_mmc1_pins {
376*4882a593Smuzhiyun		pinctrl-single,pins = <
377*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE7)		/* uart0_rtsn.gpio1_9 */
378*4882a593Smuzhiyun		>;
379*4882a593Smuzhiyun	};
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun	emmc_pwrseq_pins: pinmux_emmc_pwrseq_pins {
382*4882a593Smuzhiyun		pinctrl-single,pins = <
383*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLUP, MUX_MODE7)	/* gpmc_a4.gpio1_20 */
384*4882a593Smuzhiyun		>;
385*4882a593Smuzhiyun	};
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun	emmc_pins: pinmux_emmc_pins {
388*4882a593Smuzhiyun		pinctrl-single,pins = <
389*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2)	/* gpmc_csn1.mmc1_clk */
390*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2)	/* gpmc_csn2.mmc1_cmd */
391*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1)	/* gpmc_ad0.mmc1_dat0 */
392*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1)	/* gpmc_ad1.mmc1_dat1 */
393*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1)	/* gpmc_ad2.mmc1_dat2 */
394*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1)	/* gpmc_ad3.mmc1_dat3 */
395*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1)	/* gpmc_ad4.mmc1_dat4 */
396*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) 	/* gpmc_ad5.mmc1_dat5 */
397*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1)	/* gpmc_ad6.mmc1_dat6 */
398*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1)	/* gpmc_ad7.mmc1_dat7 */
399*4882a593Smuzhiyun		>;
400*4882a593Smuzhiyun	};
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun	ehrpwm1_pins: pinmux_ehrpwm1a_pins {
403*4882a593Smuzhiyun		pinctrl-single,pins = <
404*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE6)	/* gpmc_a2.ehrpwm1a */
405*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE6)	/* gpmc_a3.ehrpwm1b */
406*4882a593Smuzhiyun		>;
407*4882a593Smuzhiyun	};
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun	rtc0_irq_pins: pinmux_rtc0_irq_pins {
410*4882a593Smuzhiyun		pinctrl-single,pins = <
411*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE7)     /* gpmc_ad9.gpio0_23 */
412*4882a593Smuzhiyun		>;
413*4882a593Smuzhiyun	};
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun	spi0_pins: pinmux_spi0_pins {
416*4882a593Smuzhiyun		pinctrl-single,pins = <
417*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0)	/* SPI0_MOSI */
418*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0)	/* SPI0_MISO */
419*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0)
420*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)	/* SPI0_CS0 (NBATTSS) */
421*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE0)	/* SPI0_CS1 (FPGA_FLASH_NCS) */
422*4882a593Smuzhiyun		>;
423*4882a593Smuzhiyun	};
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun	lwb_pins: pinmux_lwb_pins {
426*4882a593Smuzhiyun		pinctrl-single,pins = <
427*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE7)	/* nKbdInt - gpmc_ad12.gpio1_12 */
428*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE7)	/* nKbdReset - gpmc_ad13.gpio1_13 */
429*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE7)	/* USB1_enPower - gpmc_a1.gpio1_17 */
430*4882a593Smuzhiyun			/* PDI Bus - Battery system */
431*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLUP, MUX_MODE7)	/* nBattReset  gpmc_a0.gpio1_16 */
432*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE7)	/* BattPDIData gpmc_ad15.gpio1_15 */
433*4882a593Smuzhiyun			/* FPGA */
434*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE7)	/* FPGA_DONE - gpmc_ad8.gpio0_22 */
435*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLUP, MUX_MODE7)	/* FPGA_NRST - gpmc_a0.gpio1_16 */
436*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* FPGA_RUN - gpmc_a1.gpio1_17 */
437*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLUP, MUX_MODE7)	/* ENFPGA - gpmc_a9.gpio1_25 */
438*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* FPGA_PROGRAM - gpmc_a10.gpio1_26 */
439*4882a593Smuzhiyun		>;
440*4882a593Smuzhiyun	};
441*4882a593Smuzhiyun};
442*4882a593Smuzhiyun
443*4882a593Smuzhiyun&i2c0 {
444*4882a593Smuzhiyun	status = "okay";
445*4882a593Smuzhiyun	pinctrl-names = "default";
446*4882a593Smuzhiyun	pinctrl-0 = <&i2c0_pins>;
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun	clock-frequency = <400000>;
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun	tps: tps@24 {
451*4882a593Smuzhiyun		reg = <0x24>;
452*4882a593Smuzhiyun	};
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun	rtc0: rtc@68 {
455*4882a593Smuzhiyun		compatible = "dallas,ds1339";
456*4882a593Smuzhiyun		pinctrl-names = "default";
457*4882a593Smuzhiyun		pinctrl-0 = <&rtc0_irq_pins>;
458*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
459*4882a593Smuzhiyun		interrupts = <23 IRQ_TYPE_EDGE_FALLING>; /* gpio 23 */
460*4882a593Smuzhiyun		wakeup-source;
461*4882a593Smuzhiyun		trickle-resistor-ohms = <2000>;
462*4882a593Smuzhiyun		reg = <0x68>;
463*4882a593Smuzhiyun	};
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun	eeprom: eeprom@50 {
466*4882a593Smuzhiyun		compatible = "atmel,24c256";
467*4882a593Smuzhiyun		reg = <0x50>;
468*4882a593Smuzhiyun	};
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun	gpio_exp: mcp23017@20 {
471*4882a593Smuzhiyun		compatible = "microchip,mcp23017";
472*4882a593Smuzhiyun		reg = <0x20>;
473*4882a593Smuzhiyun	};
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun};
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun&i2c2 {
478*4882a593Smuzhiyun	status = "okay";
479*4882a593Smuzhiyun	pinctrl-names = "default";
480*4882a593Smuzhiyun	pinctrl-0 = <&i2c2_pins>;
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun	clock-frequency = <400000>;
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun	audio_codec: tlv320aic3106@1b {
485*4882a593Smuzhiyun		status = "okay";
486*4882a593Smuzhiyun		compatible = "ti,tlv320aic3106";
487*4882a593Smuzhiyun		#sound-dai-cells = <0>;
488*4882a593Smuzhiyun		reg = <0x1b>;
489*4882a593Smuzhiyun		ai3x-micbias-vg = <2>;  /* 2.5V */
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun		AVDD-supply = <&ldo4_reg>;
492*4882a593Smuzhiyun		IOVDD-supply = <&ldo4_reg>;
493*4882a593Smuzhiyun		DRVDD-supply = <&ldo4_reg>;
494*4882a593Smuzhiyun		DVDD-supply = <&ldo3_reg>;
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun		codec_port: port {
497*4882a593Smuzhiyun			codec_endpoint: endpoint {
498*4882a593Smuzhiyun				remote-endpoint = <&cpu_endpoint>;
499*4882a593Smuzhiyun				clocks = <&audio_mclk>;
500*4882a593Smuzhiyun			};
501*4882a593Smuzhiyun		};
502*4882a593Smuzhiyun	};
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun	/* Ambient Light Sensor */
505*4882a593Smuzhiyun	als: isl29023@44 {
506*4882a593Smuzhiyun		compatible = "isil,isl29023";
507*4882a593Smuzhiyun		reg = <0x44>;
508*4882a593Smuzhiyun	};
509*4882a593Smuzhiyun};
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun&rtc {
512*4882a593Smuzhiyun	status = "disabled";
513*4882a593Smuzhiyun};
514*4882a593Smuzhiyun
515*4882a593Smuzhiyun&usb0 {
516*4882a593Smuzhiyun	dr_mode = "otg";
517*4882a593Smuzhiyun};
518*4882a593Smuzhiyun
519*4882a593Smuzhiyun&usb1 {
520*4882a593Smuzhiyun	dr_mode = "host";
521*4882a593Smuzhiyun};
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun&mmc1 {
524*4882a593Smuzhiyun	status = "okay";
525*4882a593Smuzhiyun	pinctrl-names = "default";
526*4882a593Smuzhiyun	pinctrl-0 = <&mmc1_pins>;
527*4882a593Smuzhiyun	bus-width = <4>;
528*4882a593Smuzhiyun	cd-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
529*4882a593Smuzhiyun	vmmc-supply = <&vmmcsd_fixed>;
530*4882a593Smuzhiyun};
531*4882a593Smuzhiyun
532*4882a593Smuzhiyun&mmc2 {
533*4882a593Smuzhiyun	status = "okay";
534*4882a593Smuzhiyun	pinctrl-names = "default";
535*4882a593Smuzhiyun	pinctrl-0 = <&emmc_pins>;
536*4882a593Smuzhiyun	bus-width = <8>;
537*4882a593Smuzhiyun	vmmc-supply = <&vmmcsd_fixed>;
538*4882a593Smuzhiyun	mmc-pwrseq = <&emmc_pwrseq>;
539*4882a593Smuzhiyun};
540*4882a593Smuzhiyun
541*4882a593Smuzhiyun&mcasp0 {
542*4882a593Smuzhiyun	status = "okay";
543*4882a593Smuzhiyun	pinctrl-names = "default";
544*4882a593Smuzhiyun	pinctrl-0 = <&audio_pins>;
545*4882a593Smuzhiyun	#sound-dai-cells = <0>;
546*4882a593Smuzhiyun	op-mode = <0>;  /* MCASP_ISS_MODE */
547*4882a593Smuzhiyun	tdm-slots = <2>;
548*4882a593Smuzhiyun	/* 4 serializers */
549*4882a593Smuzhiyun	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
550*4882a593Smuzhiyun		0 0 1 2
551*4882a593Smuzhiyun	>;
552*4882a593Smuzhiyun	tx-num-evt = <32>;
553*4882a593Smuzhiyun	rx-num-evt = <32>;
554*4882a593Smuzhiyun
555*4882a593Smuzhiyun	cpu_port: port {
556*4882a593Smuzhiyun		cpu_endpoint: endpoint {
557*4882a593Smuzhiyun			remote-endpoint = <&codec_endpoint>;
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun			dai-format = "dsp_b";
560*4882a593Smuzhiyun			bitclock-master = <&codec_port>;
561*4882a593Smuzhiyun			frame-master = <&codec_port>;
562*4882a593Smuzhiyun			bitclock-inversion;
563*4882a593Smuzhiyun			clocks = <&audio_mclk>;
564*4882a593Smuzhiyun		};
565*4882a593Smuzhiyun	};
566*4882a593Smuzhiyun};
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun&uart0 {
569*4882a593Smuzhiyun	status = "okay";
570*4882a593Smuzhiyun	pinctrl-names = "default";
571*4882a593Smuzhiyun	pinctrl-0 = <&uart0_pins>;
572*4882a593Smuzhiyun};
573*4882a593Smuzhiyun
574*4882a593Smuzhiyun&uart1 {
575*4882a593Smuzhiyun	status = "okay";
576*4882a593Smuzhiyun	pinctrl-names = "default";
577*4882a593Smuzhiyun	pinctrl-0 = <&uart1_pins>;
578*4882a593Smuzhiyun};
579*4882a593Smuzhiyun
580*4882a593Smuzhiyun&uart4 {
581*4882a593Smuzhiyun	status = "okay";
582*4882a593Smuzhiyun	pinctrl-names = "default";
583*4882a593Smuzhiyun	pinctrl-0 = <&uart4_pins>;
584*4882a593Smuzhiyun};
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun&spi0 {
587*4882a593Smuzhiyun	status = "okay";
588*4882a593Smuzhiyun	pinctrl-names = "default";
589*4882a593Smuzhiyun	pinctrl-0 = <&spi0_pins>;
590*4882a593Smuzhiyun
591*4882a593Smuzhiyun	flash: n25q032@1 {
592*4882a593Smuzhiyun		#address-cells = <1>;
593*4882a593Smuzhiyun		#size-cells = <1>;
594*4882a593Smuzhiyun		compatible = "micron,n25q032";
595*4882a593Smuzhiyun		reg = <1>;
596*4882a593Smuzhiyun		spi-max-frequency = <5000000>;
597*4882a593Smuzhiyun	};
598*4882a593Smuzhiyun};
599*4882a593Smuzhiyun
600*4882a593Smuzhiyun#include "tps65217.dtsi"
601*4882a593Smuzhiyun
602*4882a593Smuzhiyun&tps {
603*4882a593Smuzhiyun	ti,pmic-shutdown-controller;
604*4882a593Smuzhiyun
605*4882a593Smuzhiyun	interrupt-parent = <&intc>;
606*4882a593Smuzhiyun	interrupts = <7>;	/* NNMI */
607*4882a593Smuzhiyun
608*4882a593Smuzhiyun	regulators {
609*4882a593Smuzhiyun		dcdc1_reg: regulator@0 {
610*4882a593Smuzhiyun			/* VDDS_DDR */
611*4882a593Smuzhiyun			regulator-min-microvolt = <1500000>;
612*4882a593Smuzhiyun			regulator-max-microvolt = <1500000>;
613*4882a593Smuzhiyun			regulator-always-on;
614*4882a593Smuzhiyun		};
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun		dcdc2_reg: regulator@1 {
617*4882a593Smuzhiyun			/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
618*4882a593Smuzhiyun			regulator-name = "vdd_mpu";
619*4882a593Smuzhiyun			regulator-min-microvolt = <925000>;
620*4882a593Smuzhiyun			regulator-max-microvolt = <1325000>;
621*4882a593Smuzhiyun			regulator-boot-on;
622*4882a593Smuzhiyun			regulator-always-on;
623*4882a593Smuzhiyun		};
624*4882a593Smuzhiyun
625*4882a593Smuzhiyun		dcdc3_reg: regulator@2 {
626*4882a593Smuzhiyun			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
627*4882a593Smuzhiyun			regulator-name = "vdd_core";
628*4882a593Smuzhiyun			regulator-min-microvolt = <925000>;
629*4882a593Smuzhiyun			regulator-max-microvolt = <1150000>;
630*4882a593Smuzhiyun			regulator-boot-on;
631*4882a593Smuzhiyun			regulator-always-on;
632*4882a593Smuzhiyun		};
633*4882a593Smuzhiyun
634*4882a593Smuzhiyun		ldo1_reg: regulator@3 {
635*4882a593Smuzhiyun			/* VRTC / VIO / VDDS*/
636*4882a593Smuzhiyun			regulator-always-on;
637*4882a593Smuzhiyun			regulator-min-microvolt = <1800000>;
638*4882a593Smuzhiyun			regulator-max-microvolt = <1800000>;
639*4882a593Smuzhiyun		};
640*4882a593Smuzhiyun
641*4882a593Smuzhiyun		ldo2_reg: regulator@4 {
642*4882a593Smuzhiyun			/* VDD_3V3AUX */
643*4882a593Smuzhiyun			regulator-always-on;
644*4882a593Smuzhiyun			regulator-min-microvolt = <3300000>;
645*4882a593Smuzhiyun			regulator-max-microvolt = <3300000>;
646*4882a593Smuzhiyun		};
647*4882a593Smuzhiyun
648*4882a593Smuzhiyun		ldo3_reg: regulator@5 {
649*4882a593Smuzhiyun			/* VDD_1V8 */
650*4882a593Smuzhiyun			regulator-min-microvolt = <1800000>;
651*4882a593Smuzhiyun			regulator-max-microvolt = <1800000>;
652*4882a593Smuzhiyun			regulator-always-on;
653*4882a593Smuzhiyun		};
654*4882a593Smuzhiyun
655*4882a593Smuzhiyun		ldo4_reg: regulator@6 {
656*4882a593Smuzhiyun			/* VDD_3V3A */
657*4882a593Smuzhiyun			regulator-min-microvolt = <3300000>;
658*4882a593Smuzhiyun			regulator-max-microvolt = <3300000>;
659*4882a593Smuzhiyun			regulator-always-on;
660*4882a593Smuzhiyun		};
661*4882a593Smuzhiyun	};
662*4882a593Smuzhiyun};
663*4882a593Smuzhiyun
664*4882a593Smuzhiyun&cpsw_emac0 {
665*4882a593Smuzhiyun	phy-mode = "mii";
666*4882a593Smuzhiyun	phy-handle = <&ethphy0>;
667*4882a593Smuzhiyun};
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun&mac {
670*4882a593Smuzhiyun	status = "okay";
671*4882a593Smuzhiyun	pinctrl-names = "default", "sleep";
672*4882a593Smuzhiyun	pinctrl-0 = <&cpsw_default>;
673*4882a593Smuzhiyun	pinctrl-1 = <&cpsw_sleep>;
674*4882a593Smuzhiyun};
675*4882a593Smuzhiyun
676*4882a593Smuzhiyun&davinci_mdio {
677*4882a593Smuzhiyun	status = "okay";
678*4882a593Smuzhiyun	pinctrl-names = "default", "sleep";
679*4882a593Smuzhiyun	pinctrl-0 = <&davinci_mdio_default>;
680*4882a593Smuzhiyun	pinctrl-1 = <&davinci_mdio_sleep>;
681*4882a593Smuzhiyun	reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
682*4882a593Smuzhiyun	reset-delay-us = <100>;   /* PHY datasheet states 100us min */
683*4882a593Smuzhiyun
684*4882a593Smuzhiyun	ethphy0: ethernet-phy@0 {
685*4882a593Smuzhiyun		reg = <0>;
686*4882a593Smuzhiyun	};
687*4882a593Smuzhiyun};
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun&sham {
690*4882a593Smuzhiyun	status = "okay";
691*4882a593Smuzhiyun};
692*4882a593Smuzhiyun
693*4882a593Smuzhiyun&aes {
694*4882a593Smuzhiyun	status = "okay";
695*4882a593Smuzhiyun};
696*4882a593Smuzhiyun
697*4882a593Smuzhiyun&epwmss1 {
698*4882a593Smuzhiyun	status = "okay";
699*4882a593Smuzhiyun};
700*4882a593Smuzhiyun
701*4882a593Smuzhiyun&ehrpwm1 {
702*4882a593Smuzhiyun	status = "okay";
703*4882a593Smuzhiyun	pinctrl-names = "default";
704*4882a593Smuzhiyun	pinctrl-0 = <&ehrpwm1_pins>;
705*4882a593Smuzhiyun};
706*4882a593Smuzhiyun
707*4882a593Smuzhiyun&lcdc {
708*4882a593Smuzhiyun	status = "okay";
709*4882a593Smuzhiyun};
710*4882a593Smuzhiyun
711*4882a593Smuzhiyun&tscadc {
712*4882a593Smuzhiyun	status = "okay";
713*4882a593Smuzhiyun};
714*4882a593Smuzhiyun
715*4882a593Smuzhiyun&am335x_adc {
716*4882a593Smuzhiyun	ti,adc-channels = <0 1 2 3 4 5 6 7>;
717*4882a593Smuzhiyun};
718