xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/am335x-sbc-t335.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * am335x-sbc-t335.dts - Device Tree file for Compulab SBC-T335
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2014 - 2015 CompuLab Ltd. - http://www.compulab.co.il/
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun#include "am335x-cm-t335.dts"
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun/ {
11*4882a593Smuzhiyun	model = "CompuLab CM-T335 on SB-T335";
12*4882a593Smuzhiyun	compatible = "compulab,sbc-t335", "compulab,cm-t335", "ti,am33xx";
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun	/* DRM display driver */
15*4882a593Smuzhiyun	panel {
16*4882a593Smuzhiyun		compatible = "ti,tilcdc,panel";
17*4882a593Smuzhiyun		status = "okay";
18*4882a593Smuzhiyun		pinctrl-names = "default", "sleep";
19*4882a593Smuzhiyun		pinctrl-0 = <&lcd_pins_default>;
20*4882a593Smuzhiyun		pinctrl-1 = <&lcd_pins_sleep>;
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun		panel-info {
23*4882a593Smuzhiyun			ac-bias           = <255>;
24*4882a593Smuzhiyun			ac-bias-intrpt    = <0>;
25*4882a593Smuzhiyun			dma-burst-sz      = <16>;
26*4882a593Smuzhiyun			bpp               = <32>;
27*4882a593Smuzhiyun			fdd               = <0x80>;
28*4882a593Smuzhiyun			sync-edge         = <0>;
29*4882a593Smuzhiyun			sync-ctrl         = <1>;
30*4882a593Smuzhiyun			raster-order      = <0>;
31*4882a593Smuzhiyun			fifo-th           = <0>;
32*4882a593Smuzhiyun		};
33*4882a593Smuzhiyun		display-timings {
34*4882a593Smuzhiyun			/* Timing selection performed by U-Boot */
35*4882a593Smuzhiyun			timing0: lcd {/* 800x480p62 */
36*4882a593Smuzhiyun				clock-frequency = <30000000>;
37*4882a593Smuzhiyun				hactive = <800>;
38*4882a593Smuzhiyun				vactive = <480>;
39*4882a593Smuzhiyun				hfront-porch = <39>;
40*4882a593Smuzhiyun				hback-porch = <39>;
41*4882a593Smuzhiyun				hsync-len = <47>;
42*4882a593Smuzhiyun				vback-porch = <29>;
43*4882a593Smuzhiyun				vfront-porch = <13>;
44*4882a593Smuzhiyun				vsync-len = <2>;
45*4882a593Smuzhiyun				hsync-active = <1>;
46*4882a593Smuzhiyun				vsync-active = <1>;
47*4882a593Smuzhiyun			};
48*4882a593Smuzhiyun			timing1: dvi { /* 1024x768p60 */
49*4882a593Smuzhiyun				clock-frequency = <65000000>;
50*4882a593Smuzhiyun				hactive = <1024>;
51*4882a593Smuzhiyun				hfront-porch = <24>;
52*4882a593Smuzhiyun				hback-porch = <160>;
53*4882a593Smuzhiyun				hsync-len = <136>;
54*4882a593Smuzhiyun				vactive = <768>;
55*4882a593Smuzhiyun				vfront-porch = <3>;
56*4882a593Smuzhiyun				vback-porch = <29>;
57*4882a593Smuzhiyun				vsync-len = <6>;
58*4882a593Smuzhiyun				hsync-active = <0>;
59*4882a593Smuzhiyun				vsync-active = <0>;
60*4882a593Smuzhiyun			};
61*4882a593Smuzhiyun		};
62*4882a593Smuzhiyun	};
63*4882a593Smuzhiyun};
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun&am33xx_pinmux {
66*4882a593Smuzhiyun	/* Display */
67*4882a593Smuzhiyun	lcd_pins_default: lcd_pins_default {
68*4882a593Smuzhiyun		pinctrl-single,pins = <
69*4882a593Smuzhiyun			/* gpmc_ad8.lcd_data23 */
70*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1)
71*4882a593Smuzhiyun			/* gpmc_ad9.lcd_data22 */
72*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1)
73*4882a593Smuzhiyun			/* gpmc_ad10.lcd_data21 */
74*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1)
75*4882a593Smuzhiyun			/* gpmc_ad11.lcd_data20 */
76*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1)
77*4882a593Smuzhiyun			/* gpmc_ad12.lcd_data19 */
78*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1)
79*4882a593Smuzhiyun			/* gpmc_ad13.lcd_data18 */
80*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1)
81*4882a593Smuzhiyun			/* gpmc_ad14.lcd_data17 */
82*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1)
83*4882a593Smuzhiyun			/* gpmc_ad15.lcd_data16 */
84*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1)
85*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
86*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
87*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
88*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
89*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
90*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
91*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
92*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
93*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
94*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
95*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
96*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
97*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
98*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
99*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
100*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
101*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)
102*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)
103*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)
104*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)
105*4882a593Smuzhiyun		>;
106*4882a593Smuzhiyun	};
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun	lcd_pins_sleep: lcd_pins_sleep {
109*4882a593Smuzhiyun		pinctrl-single,pins = <
110*4882a593Smuzhiyun			/* gpmc_ad8.lcd_data23 */
111*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLDOWN, MUX_MODE7)
112*4882a593Smuzhiyun			/* gpmc_ad9.lcd_data22 */
113*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLDOWN, MUX_MODE7)
114*4882a593Smuzhiyun			/* gpmc_ad10.lcd_data21 */
115*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLDOWN, MUX_MODE7)
116*4882a593Smuzhiyun			/* gpmc_ad11.lcd_data20 */
117*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7)
118*4882a593Smuzhiyun			/* gpmc_ad12.lcd_data19 */
119*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLDOWN, MUX_MODE7)
120*4882a593Smuzhiyun			/* gpmc_ad13.lcd_data18 */
121*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7)
122*4882a593Smuzhiyun			/* gpmc_ad14.lcd_data17 */
123*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7)
124*4882a593Smuzhiyun			/* gpmc_ad15.lcd_data16 */
125*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7)
126*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PULL_DISABLE, MUX_MODE7)
127*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PULL_DISABLE, MUX_MODE7)
128*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PULL_DISABLE, MUX_MODE7)
129*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PULL_DISABLE, MUX_MODE7)
130*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PULL_DISABLE, MUX_MODE7)
131*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PULL_DISABLE, MUX_MODE7)
132*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PULL_DISABLE, MUX_MODE7)
133*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PULL_DISABLE, MUX_MODE7)
134*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PULL_DISABLE, MUX_MODE7)
135*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PULL_DISABLE, MUX_MODE7)
136*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PULL_DISABLE, MUX_MODE7)
137*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PULL_DISABLE, MUX_MODE7)
138*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PULL_DISABLE, MUX_MODE7)
139*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PULL_DISABLE, MUX_MODE7)
140*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PULL_DISABLE, MUX_MODE7)
141*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PULL_DISABLE, MUX_MODE7)
142*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)
143*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)
144*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
145*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
146*4882a593Smuzhiyun		>;
147*4882a593Smuzhiyun	};
148*4882a593Smuzhiyun};
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun&i2c0 {
151*4882a593Smuzhiyun	/* GPIO extender */
152*4882a593Smuzhiyun	gpio_ext: pca9555@26 {
153*4882a593Smuzhiyun		compatible = "nxp,pca9555";
154*4882a593Smuzhiyun		pinctrl-names = "default";
155*4882a593Smuzhiyun		gpio-controller;
156*4882a593Smuzhiyun		#gpio-cells = <2>;
157*4882a593Smuzhiyun		reg = <0x26>;
158*4882a593Smuzhiyun		dvi-ena-hog {
159*4882a593Smuzhiyun			gpio-hog;
160*4882a593Smuzhiyun			gpios = <13 GPIO_ACTIVE_HIGH>;
161*4882a593Smuzhiyun			output-high;
162*4882a593Smuzhiyun			line-name = "dvi-enable";
163*4882a593Smuzhiyun		};
164*4882a593Smuzhiyun		lcd-ena-hog {
165*4882a593Smuzhiyun			gpio-hog;
166*4882a593Smuzhiyun			gpios = <11 GPIO_ACTIVE_HIGH>;
167*4882a593Smuzhiyun			output-high;
168*4882a593Smuzhiyun			line-name = "lcd-enable";
169*4882a593Smuzhiyun		};
170*4882a593Smuzhiyun	};
171*4882a593Smuzhiyun};
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun/* Display */
174*4882a593Smuzhiyun&lcdc {
175*4882a593Smuzhiyun	status = "okay";
176*4882a593Smuzhiyun};
177