1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun/dts-v1/; 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include "am33xx.dtsi" 8*4882a593Smuzhiyun#include "am335x-bone-common.dtsi" 9*4882a593Smuzhiyun#include "am335x-boneblack-common.dtsi" 10*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun model = "SanCloud BeagleBone Enhanced"; 14*4882a593Smuzhiyun compatible = "sancloud,am335x-boneenhanced", "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; 15*4882a593Smuzhiyun}; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun&am33xx_pinmux { 18*4882a593Smuzhiyun pinctrl-names = "default"; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun cpsw_default: cpsw_default { 21*4882a593Smuzhiyun pinctrl-single,pins = < 22*4882a593Smuzhiyun /* Slave 1 */ 23*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ 24*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ 25*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ 26*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ 27*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ 28*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ 29*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ 30*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ 31*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ 32*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ 33*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ 34*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ 35*4882a593Smuzhiyun >; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun cpsw_sleep: cpsw_sleep { 39*4882a593Smuzhiyun pinctrl-single,pins = < 40*4882a593Smuzhiyun /* Slave 1 reset value */ 41*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) 42*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) 43*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) 44*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) 45*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) 46*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) 47*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) 48*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) 49*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) 50*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) 51*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) 52*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) 53*4882a593Smuzhiyun >; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun davinci_mdio_default: davinci_mdio_default { 57*4882a593Smuzhiyun pinctrl-single,pins = < 58*4882a593Smuzhiyun /* MDIO */ 59*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) 60*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) 61*4882a593Smuzhiyun >; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun davinci_mdio_sleep: davinci_mdio_sleep { 65*4882a593Smuzhiyun pinctrl-single,pins = < 66*4882a593Smuzhiyun /* MDIO reset value */ 67*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) 68*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) 69*4882a593Smuzhiyun >; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun usb_hub_ctrl: usb_hub_ctrl { 73*4882a593Smuzhiyun pinctrl-single,pins = < 74*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7) /* rmii1_refclk.gpio0_29 */ 75*4882a593Smuzhiyun >; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun mpu6050_pins: pinmux_mpu6050_pins { 79*4882a593Smuzhiyun pinctrl-single,pins = < 80*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE7) /* uart0_ctsn.gpio1_8 */ 81*4882a593Smuzhiyun >; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun lps3331ap_pins: pinmux_lps3331ap_pins { 85*4882a593Smuzhiyun pinctrl-single,pins = < 86*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7) /* gpmc_a10.gpio1_26 */ 87*4882a593Smuzhiyun >; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun}; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun&mac { 92*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 93*4882a593Smuzhiyun pinctrl-0 = <&cpsw_default>; 94*4882a593Smuzhiyun pinctrl-1 = <&cpsw_sleep>; 95*4882a593Smuzhiyun status = "okay"; 96*4882a593Smuzhiyun}; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun&davinci_mdio { 99*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 100*4882a593Smuzhiyun pinctrl-0 = <&davinci_mdio_default>; 101*4882a593Smuzhiyun pinctrl-1 = <&davinci_mdio_sleep>; 102*4882a593Smuzhiyun status = "okay"; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun ethphy0: ethernet-phy@0 { 105*4882a593Smuzhiyun reg = <0>; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun}; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun&cpsw_emac0 { 110*4882a593Smuzhiyun phy-handle = <ðphy0>; 111*4882a593Smuzhiyun phy-mode = "rgmii-id"; 112*4882a593Smuzhiyun}; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun&i2c0 { 115*4882a593Smuzhiyun lps331ap: barometer@5c { 116*4882a593Smuzhiyun compatible = "st,lps331ap-press"; 117*4882a593Smuzhiyun st,drdy-int-pin = <1>; 118*4882a593Smuzhiyun reg = <0x5c>; 119*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 120*4882a593Smuzhiyun interrupts = <26 IRQ_TYPE_EDGE_RISING>; 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun mpu6050: accelerometer@68 { 124*4882a593Smuzhiyun compatible = "invensense,mpu6050"; 125*4882a593Smuzhiyun reg = <0x68>; 126*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 127*4882a593Smuzhiyun interrupts = <2 IRQ_TYPE_EDGE_RISING>; 128*4882a593Smuzhiyun orientation = <0xff 0 0 0 1 0 0 0 0xff>; 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun usb2512b: usb-hub@2c { 132*4882a593Smuzhiyun compatible = "microchip,usb2512b"; 133*4882a593Smuzhiyun reg = <0x2c>; 134*4882a593Smuzhiyun reset-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; 135*4882a593Smuzhiyun /* wifi on port 4 */ 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun}; 138