1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: Robert Nelson <robertcnelson@gmail.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include "am33xx.dtsi" 10*4882a593Smuzhiyun#include "am335x-osd335x-common.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun model = "TI AM335x PocketBeagle"; 14*4882a593Smuzhiyun compatible = "ti,am335x-pocketbeagle", "ti,am335x-bone", "ti,am33xx"; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun chosen { 17*4882a593Smuzhiyun stdout-path = &uart0; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun leds { 21*4882a593Smuzhiyun pinctrl-names = "default"; 22*4882a593Smuzhiyun pinctrl-0 = <&usr_leds_pins>; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun compatible = "gpio-leds"; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun usr0 { 27*4882a593Smuzhiyun label = "beaglebone:green:usr0"; 28*4882a593Smuzhiyun gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; 29*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 30*4882a593Smuzhiyun default-state = "off"; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun usr1 { 34*4882a593Smuzhiyun label = "beaglebone:green:usr1"; 35*4882a593Smuzhiyun gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; 36*4882a593Smuzhiyun linux,default-trigger = "mmc0"; 37*4882a593Smuzhiyun default-state = "off"; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun usr2 { 41*4882a593Smuzhiyun label = "beaglebone:green:usr2"; 42*4882a593Smuzhiyun gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; 43*4882a593Smuzhiyun linux,default-trigger = "cpu0"; 44*4882a593Smuzhiyun default-state = "off"; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun usr3 { 48*4882a593Smuzhiyun label = "beaglebone:green:usr3"; 49*4882a593Smuzhiyun gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; 50*4882a593Smuzhiyun default-state = "off"; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun vmmcsd_fixed: fixedregulator0 { 55*4882a593Smuzhiyun compatible = "regulator-fixed"; 56*4882a593Smuzhiyun regulator-name = "vmmcsd_fixed"; 57*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 58*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun}; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun&gpio0 { 63*4882a593Smuzhiyun gpio-line-names = 64*4882a593Smuzhiyun "[NC]", 65*4882a593Smuzhiyun "[NC]", 66*4882a593Smuzhiyun "P1.08 [SPI0_CLK]", 67*4882a593Smuzhiyun "P1.10 [SPI0_MISO]", 68*4882a593Smuzhiyun "P1.12 [SPI0_MOSI]", 69*4882a593Smuzhiyun "P1.06 [SPI0_CS]", 70*4882a593Smuzhiyun "[MMC0_CD]", 71*4882a593Smuzhiyun "P2.29 [SPI1_CLK]", 72*4882a593Smuzhiyun "[SYSBOOT]", 73*4882a593Smuzhiyun "[SYSBOOT]", 74*4882a593Smuzhiyun "[SYSBOOT]", 75*4882a593Smuzhiyun "[SYSBOOT]", 76*4882a593Smuzhiyun "P1.26 [I2C2_SDA]", 77*4882a593Smuzhiyun "P1.28 [I2C2_SCL]", 78*4882a593Smuzhiyun "P2.11 [I2C1_SDA]", 79*4882a593Smuzhiyun "P2.09 [I2C1_SCL]", 80*4882a593Smuzhiyun "[NC]", 81*4882a593Smuzhiyun "[NC]", 82*4882a593Smuzhiyun "[NC]", 83*4882a593Smuzhiyun "P2.31 [SPI1_CS]", 84*4882a593Smuzhiyun "P1.20 [PRU0.16]", 85*4882a593Smuzhiyun "[NC]", 86*4882a593Smuzhiyun "[NC]", 87*4882a593Smuzhiyun "P2.03", 88*4882a593Smuzhiyun "[NC]", 89*4882a593Smuzhiyun "[NC]", 90*4882a593Smuzhiyun "P1.34", 91*4882a593Smuzhiyun "P2.19", 92*4882a593Smuzhiyun "[NC]", 93*4882a593Smuzhiyun "[NC]", 94*4882a593Smuzhiyun "P2.05 [UART4_RX]", 95*4882a593Smuzhiyun "P2.07 [UART4_TX]"; 96*4882a593Smuzhiyun}; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun&gpio1 { 99*4882a593Smuzhiyun gpio-line-names = 100*4882a593Smuzhiyun "[NC]", 101*4882a593Smuzhiyun "[NC]", 102*4882a593Smuzhiyun "[NC]", 103*4882a593Smuzhiyun "[NC]", 104*4882a593Smuzhiyun "[NC]", 105*4882a593Smuzhiyun "[NC]", 106*4882a593Smuzhiyun "[NC]", 107*4882a593Smuzhiyun "[NC]", 108*4882a593Smuzhiyun "[NC]", 109*4882a593Smuzhiyun "P2.25 [SPI1_MOSI]", 110*4882a593Smuzhiyun "P1.32 [UART0_RX]", 111*4882a593Smuzhiyun "P1.30 [UART0_TX]", 112*4882a593Smuzhiyun "P2.24", 113*4882a593Smuzhiyun "P2.33", 114*4882a593Smuzhiyun "P2.22", 115*4882a593Smuzhiyun "P2.18", 116*4882a593Smuzhiyun "[NC]", 117*4882a593Smuzhiyun "[NC]", 118*4882a593Smuzhiyun "P2.01 [PWM1A]", 119*4882a593Smuzhiyun "[NC]", 120*4882a593Smuzhiyun "P2.10", 121*4882a593Smuzhiyun "[USR LED 0]", 122*4882a593Smuzhiyun "[USR LED 1]", 123*4882a593Smuzhiyun "[USR LED 2]", 124*4882a593Smuzhiyun "[USR LED 3]", 125*4882a593Smuzhiyun "P2.06", 126*4882a593Smuzhiyun "P2.04", 127*4882a593Smuzhiyun "P2.02", 128*4882a593Smuzhiyun "P2.08", 129*4882a593Smuzhiyun "[NC]", 130*4882a593Smuzhiyun "[NC]", 131*4882a593Smuzhiyun "[NC]"; 132*4882a593Smuzhiyun}; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun&gpio2 { 135*4882a593Smuzhiyun gpio-line-names = 136*4882a593Smuzhiyun "P2.20", 137*4882a593Smuzhiyun "P2.17", 138*4882a593Smuzhiyun "[NC]", 139*4882a593Smuzhiyun "[NC]", 140*4882a593Smuzhiyun "[NC]", 141*4882a593Smuzhiyun "[EEPROM_WP]", 142*4882a593Smuzhiyun "[SYSBOOT]", 143*4882a593Smuzhiyun "[SYSBOOT]", 144*4882a593Smuzhiyun "[SYSBOOT]", 145*4882a593Smuzhiyun "[SYSBOOT]", 146*4882a593Smuzhiyun "[SYSBOOT]", 147*4882a593Smuzhiyun "[SYSBOOT]", 148*4882a593Smuzhiyun "[SYSBOOT]", 149*4882a593Smuzhiyun "[SYSBOOT]", 150*4882a593Smuzhiyun "[SYSBOOT]", 151*4882a593Smuzhiyun "[SYSBOOT]", 152*4882a593Smuzhiyun "[SYSBOOT]", 153*4882a593Smuzhiyun "[SYSBOOT]", 154*4882a593Smuzhiyun "[NC]", 155*4882a593Smuzhiyun "[NC]", 156*4882a593Smuzhiyun "[NC]", 157*4882a593Smuzhiyun "[NC]", 158*4882a593Smuzhiyun "P2.35 [AIN5]", 159*4882a593Smuzhiyun "P1.02 [AIN6]", 160*4882a593Smuzhiyun "P1.35 [PRU1.10]", 161*4882a593Smuzhiyun "P1.04 [PRU1.11]", 162*4882a593Smuzhiyun "[MMC0_DAT3]", 163*4882a593Smuzhiyun "[MMC0_DAT2]", 164*4882a593Smuzhiyun "[MMC0_DAT1]", 165*4882a593Smuzhiyun "[MMC0_DAT0]", 166*4882a593Smuzhiyun "[MMC0_CLK]", 167*4882a593Smuzhiyun "[MMC0_CMD]"; 168*4882a593Smuzhiyun}; 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun&gpio3 { 171*4882a593Smuzhiyun gpio-line-names = 172*4882a593Smuzhiyun "[NC]", 173*4882a593Smuzhiyun "[NC]", 174*4882a593Smuzhiyun "[NC]", 175*4882a593Smuzhiyun "[NC]", 176*4882a593Smuzhiyun "[NC]", 177*4882a593Smuzhiyun "[I2C0_SDA]", 178*4882a593Smuzhiyun "[I2C0_SCL]", 179*4882a593Smuzhiyun "[JTAG]", 180*4882a593Smuzhiyun "[JTAG]", 181*4882a593Smuzhiyun "[NC]", 182*4882a593Smuzhiyun "[NC]", 183*4882a593Smuzhiyun "[NC]", 184*4882a593Smuzhiyun "[NC]", 185*4882a593Smuzhiyun "P1.03 [USB1]", 186*4882a593Smuzhiyun "P1.36 [PWM0A]", 187*4882a593Smuzhiyun "P1.33 [PRU0.1]", 188*4882a593Smuzhiyun "P2.32 [PRU0.2]", 189*4882a593Smuzhiyun "P2.30 [PRU0.3]", 190*4882a593Smuzhiyun "P1.31 [PRU0.4]", 191*4882a593Smuzhiyun "P2.34 [PRU0.5]", 192*4882a593Smuzhiyun "P2.28 [PRU0.6]", 193*4882a593Smuzhiyun "P1.29 [PRU0.7]", 194*4882a593Smuzhiyun "[NC]", 195*4882a593Smuzhiyun "[NC]", 196*4882a593Smuzhiyun "[NC]", 197*4882a593Smuzhiyun "[NC]", 198*4882a593Smuzhiyun "[NC]", 199*4882a593Smuzhiyun "[NC]", 200*4882a593Smuzhiyun "[NC]", 201*4882a593Smuzhiyun "[NC]", 202*4882a593Smuzhiyun "[NC]", 203*4882a593Smuzhiyun "[NC]"; 204*4882a593Smuzhiyun}; 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun&am33xx_pinmux { 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun pinctrl-names = "default"; 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun pinctrl-0 = < &P2_03_gpio &P1_34_gpio &P2_19_gpio &P2_24_gpio 211*4882a593Smuzhiyun &P2_33_gpio &P2_22_gpio &P2_18_gpio &P2_10_gpio 212*4882a593Smuzhiyun &P2_06_gpio &P2_04_gpio &P2_02_gpio &P2_08_gpio 213*4882a593Smuzhiyun &P2_17_gpio >; 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun /* P2_03 (ZCZ ball T10) gpio0_23 0x824 PIN 9 */ 216*4882a593Smuzhiyun P2_03_gpio: pinmux_P2_03_gpio { 217*4882a593Smuzhiyun pinctrl-single,pins = < 218*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE7) 219*4882a593Smuzhiyun >; 220*4882a593Smuzhiyun pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; 221*4882a593Smuzhiyun pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; 222*4882a593Smuzhiyun }; 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun /* P1_34 (ZCZ ball T11) gpio0_26 0x828 PIN 10 */ 225*4882a593Smuzhiyun P1_34_gpio: pinmux_P1_34_gpio { 226*4882a593Smuzhiyun pinctrl-single,pins = < 227*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE7) 228*4882a593Smuzhiyun >; 229*4882a593Smuzhiyun pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; 230*4882a593Smuzhiyun pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; 231*4882a593Smuzhiyun }; 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun /* P2_19 (ZCZ ball U12) gpio0_27 0x82c PIN 11 */ 234*4882a593Smuzhiyun P2_19_gpio: pinmux_P2_19_gpio { 235*4882a593Smuzhiyun pinctrl-single,pins = < 236*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE7) 237*4882a593Smuzhiyun >; 238*4882a593Smuzhiyun pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; 239*4882a593Smuzhiyun pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; 240*4882a593Smuzhiyun }; 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun /* P2_24 (ZCZ ball T12) gpio1_12 0x830 PIN 12 */ 243*4882a593Smuzhiyun P2_24_gpio: pinmux_P2_24_gpio { 244*4882a593Smuzhiyun pinctrl-single,pins = < 245*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE7) 246*4882a593Smuzhiyun >; 247*4882a593Smuzhiyun pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; 248*4882a593Smuzhiyun pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; 249*4882a593Smuzhiyun }; 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun /* P2_33 (ZCZ ball R12) gpio1_13 0x834 PIN 13 */ 252*4882a593Smuzhiyun P2_33_gpio: pinmux_P2_33_gpio { 253*4882a593Smuzhiyun pinctrl-single,pins = < 254*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE7) 255*4882a593Smuzhiyun >; 256*4882a593Smuzhiyun pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; 257*4882a593Smuzhiyun pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; 258*4882a593Smuzhiyun }; 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun /* P2_22 (ZCZ ball V13) gpio1_14 0x838 PIN 14 */ 261*4882a593Smuzhiyun P2_22_gpio: pinmux_P2_22_gpio { 262*4882a593Smuzhiyun pinctrl-single,pins = < 263*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE7) 264*4882a593Smuzhiyun >; 265*4882a593Smuzhiyun pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; 266*4882a593Smuzhiyun pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; 267*4882a593Smuzhiyun }; 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun /* P2_18 (ZCZ ball U13) gpio1_15 0x83c PIN 15 */ 270*4882a593Smuzhiyun P2_18_gpio: pinmux_P2_18_gpio { 271*4882a593Smuzhiyun pinctrl-single,pins = < 272*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE7) 273*4882a593Smuzhiyun >; 274*4882a593Smuzhiyun pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; 275*4882a593Smuzhiyun pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; 276*4882a593Smuzhiyun }; 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun /* P2_10 (ZCZ ball R14) gpio1_20 0x850 PIN 20 */ 279*4882a593Smuzhiyun P2_10_gpio: pinmux_P2_10_gpio { 280*4882a593Smuzhiyun pinctrl-single,pins = < 281*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLUP, MUX_MODE7) 282*4882a593Smuzhiyun >; 283*4882a593Smuzhiyun pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; 284*4882a593Smuzhiyun pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; 285*4882a593Smuzhiyun }; 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun /* P2_06 (ZCZ ball U16) gpio1_25 0x864 PIN 25 */ 288*4882a593Smuzhiyun P2_06_gpio: pinmux_P2_06_gpio { 289*4882a593Smuzhiyun pinctrl-single,pins = < 290*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLUP, MUX_MODE7) 291*4882a593Smuzhiyun >; 292*4882a593Smuzhiyun pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; 293*4882a593Smuzhiyun pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; 294*4882a593Smuzhiyun }; 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun /* P2_04 (ZCZ ball T16) gpio1_26 0x868 PIN 26 */ 297*4882a593Smuzhiyun P2_04_gpio: pinmux_P2_04_gpio { 298*4882a593Smuzhiyun pinctrl-single,pins = < 299*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLUP, MUX_MODE7) 300*4882a593Smuzhiyun >; 301*4882a593Smuzhiyun pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; 302*4882a593Smuzhiyun pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; 303*4882a593Smuzhiyun }; 304*4882a593Smuzhiyun 305*4882a593Smuzhiyun /* P2_02 (ZCZ ball V17) gpio1_27 0x86c PIN 27 */ 306*4882a593Smuzhiyun P2_02_gpio: pinmux_P2_02_gpio { 307*4882a593Smuzhiyun pinctrl-single,pins = < 308*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLUP, MUX_MODE7) 309*4882a593Smuzhiyun >; 310*4882a593Smuzhiyun pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; 311*4882a593Smuzhiyun pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; 312*4882a593Smuzhiyun }; 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun /* P2_08 (ZCZ ball U18) gpio1_28 0x878 PIN 30 */ 315*4882a593Smuzhiyun P2_08_gpio: pinmux_P2_08_gpio { 316*4882a593Smuzhiyun pinctrl-single,pins = < 317*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE7) 318*4882a593Smuzhiyun >; 319*4882a593Smuzhiyun pinctrl-single,bias-pullup = < 0x00 0x10 0x00 0x18>; 320*4882a593Smuzhiyun pinctrl-single,bias-pulldown = < 0x00 0x00 0x10 0x18>; 321*4882a593Smuzhiyun }; 322*4882a593Smuzhiyun 323*4882a593Smuzhiyun /* P2_17 (ZCZ ball V12) gpio2_1 0x88c PIN 35 */ 324*4882a593Smuzhiyun P2_17_gpio: pinmux_P2_17_gpio { 325*4882a593Smuzhiyun pinctrl-single,pins = < 326*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE7) 327*4882a593Smuzhiyun >; 328*4882a593Smuzhiyun pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; 329*4882a593Smuzhiyun pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; 330*4882a593Smuzhiyun }; 331*4882a593Smuzhiyun 332*4882a593Smuzhiyun i2c2_pins: pinmux-i2c2-pins { 333*4882a593Smuzhiyun pinctrl-single,pins = < 334*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D17) uart1_rtsn.I2C2_SCL */ 335*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* (D18) uart1_ctsn.I2C2_SDA */ 336*4882a593Smuzhiyun >; 337*4882a593Smuzhiyun }; 338*4882a593Smuzhiyun 339*4882a593Smuzhiyun ehrpwm0_pins: pinmux-ehrpwm0-pins { 340*4882a593Smuzhiyun pinctrl-single,pins = < 341*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* (A13) mcasp0_aclkx.ehrpwm0A */ 342*4882a593Smuzhiyun >; 343*4882a593Smuzhiyun }; 344*4882a593Smuzhiyun 345*4882a593Smuzhiyun ehrpwm1_pins: pinmux-ehrpwm1-pins { 346*4882a593Smuzhiyun pinctrl-single,pins = < 347*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* (U14) gpmc_a2.ehrpwm1A */ 348*4882a593Smuzhiyun >; 349*4882a593Smuzhiyun }; 350*4882a593Smuzhiyun 351*4882a593Smuzhiyun mmc0_pins: pinmux-mmc0-pins { 352*4882a593Smuzhiyun pinctrl-single,pins = < 353*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ 354*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) 355*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) 356*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) 357*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) 358*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) 359*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) 360*4882a593Smuzhiyun >; 361*4882a593Smuzhiyun }; 362*4882a593Smuzhiyun 363*4882a593Smuzhiyun spi0_pins: pinmux-spi0-pins { 364*4882a593Smuzhiyun pinctrl-single,pins = < 365*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0) 366*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0) 367*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) 368*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0) 369*4882a593Smuzhiyun >; 370*4882a593Smuzhiyun }; 371*4882a593Smuzhiyun 372*4882a593Smuzhiyun spi1_pins: pinmux-spi1-pins { 373*4882a593Smuzhiyun pinctrl-single,pins = < 374*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE4) /* (C18) eCAP0_in_PWM0_out.spi1_sclk */ 375*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* (E18) uart0_ctsn.spi1_d0 */ 376*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* (E17) uart0_rtsn.spi1_d1 */ 377*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_INPUT_PULLUP, MUX_MODE4) /* (A15) xdma_event_intr0.spi1_cs1 */ 378*4882a593Smuzhiyun >; 379*4882a593Smuzhiyun }; 380*4882a593Smuzhiyun 381*4882a593Smuzhiyun usr_leds_pins: pinmux-usr-leds-pins { 382*4882a593Smuzhiyun pinctrl-single,pins = < 383*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7) /* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */ 384*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7) /* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */ 385*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7) /* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */ 386*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7) /* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */ 387*4882a593Smuzhiyun >; 388*4882a593Smuzhiyun }; 389*4882a593Smuzhiyun 390*4882a593Smuzhiyun uart0_pins: pinmux-uart0-pins { 391*4882a593Smuzhiyun pinctrl-single,pins = < 392*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) 393*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 394*4882a593Smuzhiyun >; 395*4882a593Smuzhiyun }; 396*4882a593Smuzhiyun 397*4882a593Smuzhiyun uart4_pins: pinmux-uart4-pins { 398*4882a593Smuzhiyun pinctrl-single,pins = < 399*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6) /* (T17) gpmc_wait0.uart4_rxd */ 400*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* (U17) gpmc_wpn.uart4_txd */ 401*4882a593Smuzhiyun >; 402*4882a593Smuzhiyun }; 403*4882a593Smuzhiyun}; 404*4882a593Smuzhiyun 405*4882a593Smuzhiyun&epwmss0 { 406*4882a593Smuzhiyun status = "okay"; 407*4882a593Smuzhiyun}; 408*4882a593Smuzhiyun 409*4882a593Smuzhiyun&ehrpwm0 { 410*4882a593Smuzhiyun status = "okay"; 411*4882a593Smuzhiyun pinctrl-names = "default"; 412*4882a593Smuzhiyun pinctrl-0 = <&ehrpwm0_pins>; 413*4882a593Smuzhiyun}; 414*4882a593Smuzhiyun 415*4882a593Smuzhiyun&epwmss1 { 416*4882a593Smuzhiyun status = "okay"; 417*4882a593Smuzhiyun}; 418*4882a593Smuzhiyun 419*4882a593Smuzhiyun&ehrpwm1 { 420*4882a593Smuzhiyun status = "okay"; 421*4882a593Smuzhiyun pinctrl-names = "default"; 422*4882a593Smuzhiyun pinctrl-0 = <&ehrpwm1_pins>; 423*4882a593Smuzhiyun}; 424*4882a593Smuzhiyun 425*4882a593Smuzhiyun&i2c0 { 426*4882a593Smuzhiyun eeprom: eeprom@50 { 427*4882a593Smuzhiyun compatible = "atmel,24c256"; 428*4882a593Smuzhiyun reg = <0x50>; 429*4882a593Smuzhiyun }; 430*4882a593Smuzhiyun}; 431*4882a593Smuzhiyun 432*4882a593Smuzhiyun&i2c2 { 433*4882a593Smuzhiyun pinctrl-names = "default"; 434*4882a593Smuzhiyun pinctrl-0 = <&i2c2_pins>; 435*4882a593Smuzhiyun 436*4882a593Smuzhiyun status = "okay"; 437*4882a593Smuzhiyun clock-frequency = <400000>; 438*4882a593Smuzhiyun}; 439*4882a593Smuzhiyun 440*4882a593Smuzhiyun&mmc1 { 441*4882a593Smuzhiyun status = "okay"; 442*4882a593Smuzhiyun vmmc-supply = <&vmmcsd_fixed>; 443*4882a593Smuzhiyun bus-width = <4>; 444*4882a593Smuzhiyun pinctrl-names = "default"; 445*4882a593Smuzhiyun pinctrl-0 = <&mmc0_pins>; 446*4882a593Smuzhiyun cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; 447*4882a593Smuzhiyun}; 448*4882a593Smuzhiyun 449*4882a593Smuzhiyun&rtc { 450*4882a593Smuzhiyun system-power-controller; 451*4882a593Smuzhiyun}; 452*4882a593Smuzhiyun 453*4882a593Smuzhiyun&tscadc { 454*4882a593Smuzhiyun status = "okay"; 455*4882a593Smuzhiyun adc { 456*4882a593Smuzhiyun ti,adc-channels = <0 1 2 3 4 5 6 7>; 457*4882a593Smuzhiyun ti,chan-step-avg = <16 16 16 16 16 16 16 16>; 458*4882a593Smuzhiyun ti,chan-step-opendelay = <0x98 0x98 0x98 0x98 0x98 0x98 0x98 0x98>; 459*4882a593Smuzhiyun ti,chan-step-sampledelay = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; 460*4882a593Smuzhiyun }; 461*4882a593Smuzhiyun}; 462*4882a593Smuzhiyun 463*4882a593Smuzhiyun&uart0 { 464*4882a593Smuzhiyun pinctrl-names = "default"; 465*4882a593Smuzhiyun pinctrl-0 = <&uart0_pins>; 466*4882a593Smuzhiyun 467*4882a593Smuzhiyun status = "okay"; 468*4882a593Smuzhiyun}; 469*4882a593Smuzhiyun 470*4882a593Smuzhiyun&uart4 { 471*4882a593Smuzhiyun pinctrl-names = "default"; 472*4882a593Smuzhiyun pinctrl-0 = <&uart4_pins>; 473*4882a593Smuzhiyun 474*4882a593Smuzhiyun status = "okay"; 475*4882a593Smuzhiyun}; 476*4882a593Smuzhiyun 477*4882a593Smuzhiyun&usb0 { 478*4882a593Smuzhiyun dr_mode = "otg"; 479*4882a593Smuzhiyun}; 480*4882a593Smuzhiyun 481*4882a593Smuzhiyun&usb1 { 482*4882a593Smuzhiyun dr_mode = "host"; 483*4882a593Smuzhiyun}; 484