xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/am335x-pcm-953.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (C) 2014-2017 Phytec Messtechnik GmbH
4*4882a593Smuzhiyun * Author: Wadim Egorov <w.egorov@phytec.de>
5*4882a593Smuzhiyun *	   Teresa Remmet <t.remmet@phytec.de>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun/ {
11*4882a593Smuzhiyun	model = "Phytec AM335x PCM-953";
12*4882a593Smuzhiyun	compatible = "phytec,am335x-pcm-953", "phytec,am335x-phycore-som", "ti,am33xx";
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun	/* Power */
15*4882a593Smuzhiyun	vcc3v3: fixedregulator1 {
16*4882a593Smuzhiyun		compatible = "regulator-fixed";
17*4882a593Smuzhiyun		regulator-name = "vcc3v3";
18*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
19*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
20*4882a593Smuzhiyun		regulator-boot-on;
21*4882a593Smuzhiyun	};
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun	vcc1v8: fixedregulator2 {
24*4882a593Smuzhiyun		compatible = "regulator-fixed";
25*4882a593Smuzhiyun		regulator-name = "vcc1v8";
26*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
27*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
28*4882a593Smuzhiyun		regulator-boot-on;
29*4882a593Smuzhiyun	};
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun	/* User IO */
32*4882a593Smuzhiyun	user_leds: user_leds {
33*4882a593Smuzhiyun		compatible = "gpio-leds";
34*4882a593Smuzhiyun		pinctrl-names = "default";
35*4882a593Smuzhiyun		pinctrl-0 = <&user_leds_pins>;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun		user-led0 {
38*4882a593Smuzhiyun			gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
39*4882a593Smuzhiyun			linux,default-trigger = "gpio";
40*4882a593Smuzhiyun			default-state = "on";
41*4882a593Smuzhiyun		};
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun		user-led1 {
44*4882a593Smuzhiyun			gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
45*4882a593Smuzhiyun			linux,default-trigger = "gpio";
46*4882a593Smuzhiyun			default-state = "on";
47*4882a593Smuzhiyun		};
48*4882a593Smuzhiyun	};
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun	user_buttons: user_buttons {
51*4882a593Smuzhiyun		compatible = "gpio-keys";
52*4882a593Smuzhiyun		pinctrl-names = "default";
53*4882a593Smuzhiyun		pinctrl-0 = <&user_buttons_pins>;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun		button@0 {
56*4882a593Smuzhiyun			label = "home";
57*4882a593Smuzhiyun			linux,code = <KEY_HOME>;
58*4882a593Smuzhiyun			gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;
59*4882a593Smuzhiyun			wakeup-source;
60*4882a593Smuzhiyun		};
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun		button@1 {
63*4882a593Smuzhiyun			label = "menu";
64*4882a593Smuzhiyun			linux,code = <KEY_MENU>;
65*4882a593Smuzhiyun			gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
66*4882a593Smuzhiyun			wakeup-source;
67*4882a593Smuzhiyun		};
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun	};
70*4882a593Smuzhiyun};
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun&am33xx_pinmux {
73*4882a593Smuzhiyun	user_buttons_pins: pinmux_user_buttons {
74*4882a593Smuzhiyun		pinctrl-single,pins = <
75*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* emu0.gpio3_7 */
76*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_INPUT_PULLDOWN, MUX_MODE7)	/* emu1.gpio3_8 */
77*4882a593Smuzhiyun		>;
78*4882a593Smuzhiyun	};
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun	user_leds_pins: pinmux_user_leds {
81*4882a593Smuzhiyun		pinctrl-single,pins = <
82*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* gpmc_csn1.gpio1_30 */
83*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* gpmc_csn2.gpio1_31 */
84*4882a593Smuzhiyun		>;
85*4882a593Smuzhiyun	};
86*4882a593Smuzhiyun};
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun/* CAN */
89*4882a593Smuzhiyun&am33xx_pinmux {
90*4882a593Smuzhiyun	dcan1_pins: pinmux_dcan1 {
91*4882a593Smuzhiyun		pinctrl-single,pins = <
92*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_OUTPUT_PULLUP, MUX_MODE2)	/* uart1_rxd.dcan1_tx_mux2 */
93*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT_PULLUP, MUX_MODE2)	/* uart1_txd.dcan1_rx_mux2 */
94*4882a593Smuzhiyun		>;
95*4882a593Smuzhiyun	};
96*4882a593Smuzhiyun};
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun&dcan1 {
99*4882a593Smuzhiyun	pinctrl-names = "default";
100*4882a593Smuzhiyun	pinctrl-0 = <&dcan1_pins>;
101*4882a593Smuzhiyun	status = "okay";
102*4882a593Smuzhiyun};
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun/* Ethernet */
105*4882a593Smuzhiyun&am33xx_pinmux {
106*4882a593Smuzhiyun	ethernet1_pins: pinmux_ethernet1 {
107*4882a593Smuzhiyun		pinctrl-single,pins = <
108*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a0.rgmii2_tctl */
109*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a1.rgmii2_rctl */
110*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a2.rgmii2_td3 */
111*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a3.rgmii2_td2 */
112*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a4.rgmii2_td1 */
113*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a5.rgmii2_td0 */
114*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a6.rgmii2_tclk */
115*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a7.rgmii2_rclk */
116*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a8.rgmii2_rd3 */
117*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a9.rgmii2_rd2 */
118*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a10.rgmii2_rd1 */
119*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2)	/* gpmc_a11.rgmii2_rd0 */
120*4882a593Smuzhiyun		>;
121*4882a593Smuzhiyun	};
122*4882a593Smuzhiyun};
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun&cpsw_emac1 {
125*4882a593Smuzhiyun	phy-handle = <&phy1>;
126*4882a593Smuzhiyun	phy-mode = "rgmii-id";
127*4882a593Smuzhiyun	dual_emac_res_vlan = <2>;
128*4882a593Smuzhiyun	status = "okay";
129*4882a593Smuzhiyun};
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun&davinci_mdio {
132*4882a593Smuzhiyun	phy1: ethernet-phy@2 {
133*4882a593Smuzhiyun		reg = <2>;
134*4882a593Smuzhiyun	};
135*4882a593Smuzhiyun};
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun&mac {
138*4882a593Smuzhiyun	slaves = <2>;
139*4882a593Smuzhiyun	pinctrl-names = "default";
140*4882a593Smuzhiyun	pinctrl-0 = <&ethernet0_pins &ethernet1_pins>;
141*4882a593Smuzhiyun	dual_emac;
142*4882a593Smuzhiyun};
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun/* Misc */
145*4882a593Smuzhiyun&am33xx_pinmux {
146*4882a593Smuzhiyun	pinctrl-names = "default";
147*4882a593Smuzhiyun	pinctrl-0 = <&cb_gpio_pins>;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun	cb_gpio_pins: pinmux_cb_gpio {
150*4882a593Smuzhiyun		pinctrl-single,pins = <
151*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* uart0_ctsn.gpio1_8 */
152*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE7)	/* uart0_rtsn.gpio1_9 */
153*4882a593Smuzhiyun		>;
154*4882a593Smuzhiyun	};
155*4882a593Smuzhiyun};
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun/* MMC */
158*4882a593Smuzhiyun&am33xx_pinmux {
159*4882a593Smuzhiyun	mmc1_pins: pinmux_mmc1_pins {
160*4882a593Smuzhiyun		pinctrl-single,pins = <
161*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
162*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
163*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
164*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
165*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
166*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
167*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7)	/* spi0_cs1.mmc0_sdcd */
168*4882a593Smuzhiyun		>;
169*4882a593Smuzhiyun	};
170*4882a593Smuzhiyun};
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun&mmc1 {
173*4882a593Smuzhiyun	vmmc-supply = <&vcc3v3>;
174*4882a593Smuzhiyun	bus-width = <4>;
175*4882a593Smuzhiyun	pinctrl-names = "default";
176*4882a593Smuzhiyun	pinctrl-0 = <&mmc1_pins>;
177*4882a593Smuzhiyun	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
178*4882a593Smuzhiyun	status = "okay";
179*4882a593Smuzhiyun};
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun/* UARTs */
182*4882a593Smuzhiyun&am33xx_pinmux {
183*4882a593Smuzhiyun	uart0_pins: pinmux_uart0 {
184*4882a593Smuzhiyun		pinctrl-single,pins = <
185*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
186*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
187*4882a593Smuzhiyun		>;
188*4882a593Smuzhiyun	};
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun	uart1_pins: pinmux_uart1 {
191*4882a593Smuzhiyun		pinctrl-single,pins = <
192*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
193*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
194*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0)
195*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
196*4882a593Smuzhiyun		>;
197*4882a593Smuzhiyun	};
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun	uart2_pins: pinmux_uart2 {
200*4882a593Smuzhiyun		pinctrl-single,pins = <
201*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1)	/* mii1_tx_clk.uart2_rxd */
202*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1)	/* mii1_rx_clk.uart2_txd */
203*4882a593Smuzhiyun		>;
204*4882a593Smuzhiyun	};
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun	uart3_pins: pinmux_uart3 {
207*4882a593Smuzhiyun		pinctrl-single,pins = <
208*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1)	/* mii1_rxd3.uart3_rxd */
209*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1)	/* mii1_rxd2.uart3_txd */
210*4882a593Smuzhiyun		>;
211*4882a593Smuzhiyun	};
212*4882a593Smuzhiyun};
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun&uart0 {
215*4882a593Smuzhiyun	pinctrl-names = "default";
216*4882a593Smuzhiyun	pinctrl-0 = <&uart0_pins>;
217*4882a593Smuzhiyun	status = "okay";
218*4882a593Smuzhiyun};
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun&uart1 {
221*4882a593Smuzhiyun	pinctrl-names = "default";
222*4882a593Smuzhiyun	pinctrl-0 = <&uart1_pins>;
223*4882a593Smuzhiyun};
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun&uart2 {
226*4882a593Smuzhiyun	pinctrl-names = "default";
227*4882a593Smuzhiyun	pinctrl-0 = <&uart2_pins>;
228*4882a593Smuzhiyun	status = "okay";
229*4882a593Smuzhiyun};
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun&uart3 {
232*4882a593Smuzhiyun	pinctrl-names = "default";
233*4882a593Smuzhiyun	pinctrl-0 = <&uart3_pins>;
234*4882a593Smuzhiyun	status = "okay";
235*4882a593Smuzhiyun};
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun/* USB */
238*4882a593Smuzhiyun&usb1 {
239*4882a593Smuzhiyun	dr_mode = "host";
240*4882a593Smuzhiyun};
241