xref: /OK3568_Linux_fs/kernel/arch/arm/boot/dts/am335x-osd335x-common.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Author: Robert Nelson <robertcnelson@gmail.com>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun/ {
9*4882a593Smuzhiyun	cpus {
10*4882a593Smuzhiyun		cpu@0 {
11*4882a593Smuzhiyun			cpu0-supply = <&dcdc2_reg>;
12*4882a593Smuzhiyun		};
13*4882a593Smuzhiyun	};
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun	memory@80000000 {
16*4882a593Smuzhiyun		device_type = "memory";
17*4882a593Smuzhiyun		reg = <0x80000000 0x20000000>; /* 512 MB */
18*4882a593Smuzhiyun	};
19*4882a593Smuzhiyun};
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun&cpu0_opp_table {
22*4882a593Smuzhiyun	/*
23*4882a593Smuzhiyun	* Octavo Systems:
24*4882a593Smuzhiyun	* The EFUSE_SMA register is not programmed for any of the AM335x wafers
25*4882a593Smuzhiyun	* we get and we are not programming them during our production test.
26*4882a593Smuzhiyun	* Therefore, from a DEVICE_ID revision point of view, the silicon looks
27*4882a593Smuzhiyun	* like it is Revision 2.1.  However, from an EFUSE_SMA point of view for
28*4882a593Smuzhiyun	* the HW OPP table, the silicon looks like it is Revision 1.0 (ie the
29*4882a593Smuzhiyun	* EFUSE_SMA register reads as all zeros).
30*4882a593Smuzhiyun	*/
31*4882a593Smuzhiyun	oppnitro-1000000000 {
32*4882a593Smuzhiyun		opp-supported-hw = <0x06 0x0100>;
33*4882a593Smuzhiyun	};
34*4882a593Smuzhiyun};
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun&am33xx_pinmux {
37*4882a593Smuzhiyun	i2c0_pins: pinmux-i2c0-pins {
38*4882a593Smuzhiyun		pinctrl-single,pins = <
39*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
40*4882a593Smuzhiyun			AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
41*4882a593Smuzhiyun		>;
42*4882a593Smuzhiyun	};
43*4882a593Smuzhiyun};
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun&i2c0 {
46*4882a593Smuzhiyun	pinctrl-names = "default";
47*4882a593Smuzhiyun	pinctrl-0 = <&i2c0_pins>;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun	status = "okay";
50*4882a593Smuzhiyun	clock-frequency = <400000>;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun	tps: tps@24 {
53*4882a593Smuzhiyun		reg = <0x24>;
54*4882a593Smuzhiyun	};
55*4882a593Smuzhiyun};
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun/include/ "tps65217.dtsi"
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun&tps {
60*4882a593Smuzhiyun	interrupts = <7>; /* NMI */
61*4882a593Smuzhiyun	interrupt-parent = <&intc>;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun	ti,pmic-shutdown-controller;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun	pwrbutton {
66*4882a593Smuzhiyun		interrupts = <2>;
67*4882a593Smuzhiyun		status = "okay";
68*4882a593Smuzhiyun	};
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun	regulators {
71*4882a593Smuzhiyun		dcdc1_reg: regulator@0 {
72*4882a593Smuzhiyun			regulator-name = "vdds_dpr";
73*4882a593Smuzhiyun			regulator-always-on;
74*4882a593Smuzhiyun		};
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun		dcdc2_reg: regulator@1 {
77*4882a593Smuzhiyun			/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
78*4882a593Smuzhiyun			regulator-name = "vdd_mpu";
79*4882a593Smuzhiyun			regulator-min-microvolt = <925000>;
80*4882a593Smuzhiyun			regulator-max-microvolt = <1351500>;
81*4882a593Smuzhiyun			regulator-boot-on;
82*4882a593Smuzhiyun			regulator-always-on;
83*4882a593Smuzhiyun		};
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun		dcdc3_reg: regulator@2 {
86*4882a593Smuzhiyun			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
87*4882a593Smuzhiyun			regulator-name = "vdd_core";
88*4882a593Smuzhiyun			regulator-min-microvolt = <925000>;
89*4882a593Smuzhiyun			regulator-max-microvolt = <1150000>;
90*4882a593Smuzhiyun			regulator-boot-on;
91*4882a593Smuzhiyun			regulator-always-on;
92*4882a593Smuzhiyun		};
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun		ldo1_reg: regulator@3 {
95*4882a593Smuzhiyun			regulator-name = "vio,vrtc,vdds";
96*4882a593Smuzhiyun			regulator-always-on;
97*4882a593Smuzhiyun		};
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun		ldo2_reg: regulator@4 {
100*4882a593Smuzhiyun			regulator-name = "vdd_3v3aux";
101*4882a593Smuzhiyun			regulator-always-on;
102*4882a593Smuzhiyun		};
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun		ldo3_reg: regulator@5 {
105*4882a593Smuzhiyun			regulator-name = "vdd_1v8";
106*4882a593Smuzhiyun			regulator-min-microvolt = <1800000>;
107*4882a593Smuzhiyun			regulator-max-microvolt = <1800000>;
108*4882a593Smuzhiyun			regulator-always-on;
109*4882a593Smuzhiyun		};
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun		ldo4_reg: regulator@6 {
112*4882a593Smuzhiyun			regulator-name = "vdd_3v3a";
113*4882a593Smuzhiyun			regulator-always-on;
114*4882a593Smuzhiyun		};
115*4882a593Smuzhiyun	};
116*4882a593Smuzhiyun};
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun&aes {
119*4882a593Smuzhiyun	status = "okay";
120*4882a593Smuzhiyun};
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun&sham {
123*4882a593Smuzhiyun	status = "okay";
124*4882a593Smuzhiyun};
125