1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2018 MOXA Inc. - https://www.moxa.com/ 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Authors: SZ Lin (林上智) <sz.lin@moxa.com> 6*4882a593Smuzhiyun * Wes Huang (黃淵河) <wes.huang@moxa.com> 7*4882a593Smuzhiyun * Fero JD Zhou (周俊達) <FeroJD.Zhou@moxa.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/dts-v1/; 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun#include "am335x-moxa-uc-2100-common.dtsi" 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun/ { 15*4882a593Smuzhiyun model = "Moxa UC-2101"; 16*4882a593Smuzhiyun compatible = "moxa,uc-2101", "ti,am33xx"; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun leds { 19*4882a593Smuzhiyun compatible = "gpio-leds"; 20*4882a593Smuzhiyun led1 { 21*4882a593Smuzhiyun label = "UC2100:GREEN:USER"; 22*4882a593Smuzhiyun gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>; 23*4882a593Smuzhiyun default-state = "off"; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun}; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun&am33xx_pinmux { 29*4882a593Smuzhiyun pinctrl-names = "default"; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun cpsw_default: cpsw_default { 32*4882a593Smuzhiyun pinctrl-single,pins = < 33*4882a593Smuzhiyun /* Slave 1 */ 34*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ 35*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ 36*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txen.rmii1_txen */ 37*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ 38*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ 39*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ 40*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ 41*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) 42*4882a593Smuzhiyun >; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun spi1_pins: pinmux_spi1 { 46*4882a593Smuzhiyun pinctrl-single,pins = < 47*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE4) /* ecap0_in_pwm0_out.spi1_sclk */ 48*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* uart1_ctsn.spi1_cs0 */ 49*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* uart0_ctsn.spi1_d0 */ 50*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE4) /* uart0_rtsn.spi1_d1 */ 51*4882a593Smuzhiyun >; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun}; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun&davinci_mdio { 56*4882a593Smuzhiyun phy0: ethernet-phy@4 { 57*4882a593Smuzhiyun reg = <4>; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun}; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun&cpsw_emac0 { 62*4882a593Smuzhiyun status = "okay"; 63*4882a593Smuzhiyun phy-handle = <&phy0>; 64*4882a593Smuzhiyun phy-mode = "rmii"; 65*4882a593Smuzhiyun}; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun&cpsw_emac1 { 68*4882a593Smuzhiyun status = "disabled"; 69*4882a593Smuzhiyun}; 70