1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2014 NovaTech LLC - https://www.novatechweb.com 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun/dts-v1/; 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include "am33xx.dtsi" 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/ { 10*4882a593Smuzhiyun model = "NovaTech OrionLXm"; 11*4882a593Smuzhiyun compatible = "novatech,am335x-lxm", "ti,am33xx"; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun cpus { 14*4882a593Smuzhiyun cpu@0 { 15*4882a593Smuzhiyun cpu0-supply = <&vdd1_reg>; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun memory@80000000 { 20*4882a593Smuzhiyun device_type = "memory"; 21*4882a593Smuzhiyun reg = <0x80000000 0x20000000>; /* 512 MB */ 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* Power supply provides a fixed 5V @2A */ 25*4882a593Smuzhiyun vbat: fixedregulator0 { 26*4882a593Smuzhiyun compatible = "regulator-fixed"; 27*4882a593Smuzhiyun regulator-name = "vbat"; 28*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 29*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 30*4882a593Smuzhiyun regulator-boot-on; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* Power supply provides a fixed 3.3V @3A */ 34*4882a593Smuzhiyun vmmcsd_fixed: fixedregulator1 { 35*4882a593Smuzhiyun compatible = "regulator-fixed"; 36*4882a593Smuzhiyun regulator-name = "vmmcsd_fixed"; 37*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 38*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 39*4882a593Smuzhiyun regulator-boot-on; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun}; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun&am33xx_pinmux { 44*4882a593Smuzhiyun mmc1_pins: pinmux_mmc1_pins { 45*4882a593Smuzhiyun pinctrl-single,pins = < 46*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) 47*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) 48*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) 49*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) 50*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) 51*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) 52*4882a593Smuzhiyun >; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun i2c0_pins: pinmux_i2c0_pins { 56*4882a593Smuzhiyun pinctrl-single,pins = < 57*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0) 58*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0) 59*4882a593Smuzhiyun >; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun cpsw_default: cpsw_default { 63*4882a593Smuzhiyun pinctrl-single,pins = < 64*4882a593Smuzhiyun /* Slave 1 */ 65*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_int */ 66*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_crs_dv */ 67*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_rxer */ 68*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* rmii1_txen */ 69*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* rmii1_td1 */ 70*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* rmii1_td0 */ 71*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_rd1 */ 72*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii1_rd0 */ 73*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0) 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* Slave 2 */ 76*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_txen */ 77*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td1 */ 78*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td0 */ 79*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd1 */ 80*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd0 */ 81*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_crs_dv */ 82*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rxer */ 83*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_int */ 84*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii2_refclk */ 85*4882a593Smuzhiyun >; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun cpsw_sleep: cpsw_sleep { 89*4882a593Smuzhiyun pinctrl-single,pins = < 90*4882a593Smuzhiyun /* Slave 1 reset value */ 91*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_int */ 92*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_crs_dv */ 93*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_rxer */ 94*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_txen */ 95*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_td1 */ 96*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_td0 */ 97*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_rd1 */ 98*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_rd0 */ 99*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_refclk */ 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun /* Slave 2 reset value*/ 102*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_txen */ 103*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_td1 */ 104*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_td0 */ 105*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_rd1 */ 106*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_rd0 */ 107*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_crs_dv */ 108*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_rxer */ 109*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_int */ 110*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii2_refclk */ 111*4882a593Smuzhiyun >; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun davinci_mdio_default: davinci_mdio_default { 115*4882a593Smuzhiyun pinctrl-single,pins = < 116*4882a593Smuzhiyun /* MDIO */ 117*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) 118*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) 119*4882a593Smuzhiyun >; 120*4882a593Smuzhiyun }; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun davinci_mdio_sleep: davinci_mdio_sleep { 123*4882a593Smuzhiyun pinctrl-single,pins = < 124*4882a593Smuzhiyun /* MDIO reset value */ 125*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) 126*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) 127*4882a593Smuzhiyun >; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun emmc_pins: pinmux_emmc_pins { 131*4882a593Smuzhiyun pinctrl-single,pins = < 132*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ 133*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ 134*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ 135*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ 136*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ 137*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ 138*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ 139*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ 140*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ 141*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ 142*4882a593Smuzhiyun >; 143*4882a593Smuzhiyun }; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun uart0_pins: pinmux_uart0_pins { 146*4882a593Smuzhiyun pinctrl-single,pins = < 147*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) 148*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 149*4882a593Smuzhiyun >; 150*4882a593Smuzhiyun }; 151*4882a593Smuzhiyun}; 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun&i2c0 { 154*4882a593Smuzhiyun pinctrl-names = "default"; 155*4882a593Smuzhiyun pinctrl-0 = <&i2c0_pins>; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun status = "okay"; 158*4882a593Smuzhiyun clock-frequency = <400000>; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun serial_config1: serial_config1@20 { 161*4882a593Smuzhiyun compatible = "nxp,pca9539"; 162*4882a593Smuzhiyun reg = <0x20>; 163*4882a593Smuzhiyun gpio-controller; 164*4882a593Smuzhiyun #gpio-cells = <2>; 165*4882a593Smuzhiyun }; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun serial_config2: serial_config2@21 { 168*4882a593Smuzhiyun compatible = "nxp,pca9539"; 169*4882a593Smuzhiyun reg = <0x21>; 170*4882a593Smuzhiyun gpio-controller; 171*4882a593Smuzhiyun #gpio-cells = <2>; 172*4882a593Smuzhiyun }; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun tps: tps@2d { 175*4882a593Smuzhiyun compatible = "ti,tps65910"; 176*4882a593Smuzhiyun reg = <0x2d>; 177*4882a593Smuzhiyun }; 178*4882a593Smuzhiyun}; 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun/include/ "tps65910.dtsi" 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun&tps { 183*4882a593Smuzhiyun vcc1-supply = <&vbat>; 184*4882a593Smuzhiyun vcc2-supply = <&vbat>; 185*4882a593Smuzhiyun vcc3-supply = <&vbat>; 186*4882a593Smuzhiyun vcc4-supply = <&vbat>; 187*4882a593Smuzhiyun vcc5-supply = <&vbat>; 188*4882a593Smuzhiyun vcc6-supply = <&vbat>; 189*4882a593Smuzhiyun vcc7-supply = <&vbat>; 190*4882a593Smuzhiyun vccio-supply = <&vbat>; 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun regulators { 193*4882a593Smuzhiyun /* vrtc - unused */ 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun vio_reg: regulator@1 { 196*4882a593Smuzhiyun regulator-name = "vio_1v5,ddr"; 197*4882a593Smuzhiyun regulator-min-microvolt = <1500000>; 198*4882a593Smuzhiyun regulator-max-microvolt = <1500000>; 199*4882a593Smuzhiyun regulator-boot-on; 200*4882a593Smuzhiyun regulator-always-on; 201*4882a593Smuzhiyun }; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun vdd1_reg: regulator@2 { 204*4882a593Smuzhiyun regulator-name = "vdd1,mpu"; 205*4882a593Smuzhiyun regulator-min-microvolt = <600000>; 206*4882a593Smuzhiyun regulator-max-microvolt = <1500000>; 207*4882a593Smuzhiyun regulator-boot-on; 208*4882a593Smuzhiyun regulator-always-on; 209*4882a593Smuzhiyun }; 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun vdd2_reg: regulator@3 { 212*4882a593Smuzhiyun regulator-name = "vdd2_1v1,core"; 213*4882a593Smuzhiyun regulator-min-microvolt = <1100000>; 214*4882a593Smuzhiyun regulator-max-microvolt = <1100000>; 215*4882a593Smuzhiyun regulator-boot-on; 216*4882a593Smuzhiyun regulator-always-on; 217*4882a593Smuzhiyun }; 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun /* vdd3 - unused */ 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun /* vdig1 - unused */ 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun vdig2_reg: regulator@6 { 224*4882a593Smuzhiyun regulator-name = "vdig2_1v8,vdds_pll"; 225*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 226*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 227*4882a593Smuzhiyun regulator-boot-on; 228*4882a593Smuzhiyun regulator-always-on; 229*4882a593Smuzhiyun }; 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun /* vpll - unused */ 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun vdac_reg: regulator@8 { 234*4882a593Smuzhiyun regulator-name = "vdac_1v8,vdds"; 235*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 236*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 237*4882a593Smuzhiyun regulator-boot-on; 238*4882a593Smuzhiyun regulator-always-on; 239*4882a593Smuzhiyun }; 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun vaux1_reg: regulator@9 { 242*4882a593Smuzhiyun regulator-name = "vaux1_1v8,usb"; 243*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 244*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 245*4882a593Smuzhiyun regulator-boot-on; 246*4882a593Smuzhiyun regulator-always-on; 247*4882a593Smuzhiyun }; 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun vaux2_reg: regulator@10 { 250*4882a593Smuzhiyun regulator-name = "vaux2_3v3,io"; 251*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 252*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 253*4882a593Smuzhiyun regulator-boot-on; 254*4882a593Smuzhiyun regulator-always-on; 255*4882a593Smuzhiyun }; 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun vaux33_reg: regulator@11 { 258*4882a593Smuzhiyun regulator-name = "vaux33_3v3,usb"; 259*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 260*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 261*4882a593Smuzhiyun regulator-boot-on; 262*4882a593Smuzhiyun regulator-always-on; 263*4882a593Smuzhiyun }; 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun vmmc_reg: regulator@12 { 266*4882a593Smuzhiyun regulator-name = "vmmc_3v3,io"; 267*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 268*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 269*4882a593Smuzhiyun regulator-boot-on; 270*4882a593Smuzhiyun regulator-always-on; 271*4882a593Smuzhiyun }; 272*4882a593Smuzhiyun }; 273*4882a593Smuzhiyun}; 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun&sham { 276*4882a593Smuzhiyun status = "okay"; 277*4882a593Smuzhiyun}; 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun&aes { 280*4882a593Smuzhiyun status = "okay"; 281*4882a593Smuzhiyun}; 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun&uart0 { 284*4882a593Smuzhiyun pinctrl-names = "default"; 285*4882a593Smuzhiyun pinctrl-0 = <&uart0_pins>; 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun status = "okay"; 288*4882a593Smuzhiyun}; 289*4882a593Smuzhiyun 290*4882a593Smuzhiyun&usb0 { 291*4882a593Smuzhiyun dr_mode = "host"; 292*4882a593Smuzhiyun}; 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun&usb1 { 295*4882a593Smuzhiyun dr_mode = "host"; 296*4882a593Smuzhiyun}; 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun&cpsw_emac0 { 299*4882a593Smuzhiyun phy-handle = <ðphy0>; 300*4882a593Smuzhiyun phy-mode = "rmii"; 301*4882a593Smuzhiyun dual_emac_res_vlan = <2>; 302*4882a593Smuzhiyun}; 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun&cpsw_emac1 { 305*4882a593Smuzhiyun phy-handle = <ðphy1>; 306*4882a593Smuzhiyun phy-mode = "rmii"; 307*4882a593Smuzhiyun dual_emac_res_vlan = <3>; 308*4882a593Smuzhiyun}; 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun&mac { 311*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 312*4882a593Smuzhiyun pinctrl-0 = <&cpsw_default>; 313*4882a593Smuzhiyun pinctrl-1 = <&cpsw_sleep>; 314*4882a593Smuzhiyun dual_emac = <1>; 315*4882a593Smuzhiyun status = "okay"; 316*4882a593Smuzhiyun}; 317*4882a593Smuzhiyun 318*4882a593Smuzhiyun&davinci_mdio { 319*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 320*4882a593Smuzhiyun pinctrl-0 = <&davinci_mdio_default>; 321*4882a593Smuzhiyun pinctrl-1 = <&davinci_mdio_sleep>; 322*4882a593Smuzhiyun status = "okay"; 323*4882a593Smuzhiyun 324*4882a593Smuzhiyun ethphy0: ethernet-phy@5 { 325*4882a593Smuzhiyun reg = <5>; 326*4882a593Smuzhiyun }; 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun ethphy1: ethernet-phy@4 { 329*4882a593Smuzhiyun reg = <4>; 330*4882a593Smuzhiyun }; 331*4882a593Smuzhiyun}; 332*4882a593Smuzhiyun 333*4882a593Smuzhiyun&mmc1 { 334*4882a593Smuzhiyun pinctrl-names = "default"; 335*4882a593Smuzhiyun pinctrl-0 = <&mmc1_pins>; 336*4882a593Smuzhiyun vmmc-supply = <&vmmcsd_fixed>; 337*4882a593Smuzhiyun bus-width = <4>; 338*4882a593Smuzhiyun status = "okay"; 339*4882a593Smuzhiyun}; 340*4882a593Smuzhiyun 341*4882a593Smuzhiyun&mmc2 { 342*4882a593Smuzhiyun pinctrl-names = "default"; 343*4882a593Smuzhiyun pinctrl-0 = <&emmc_pins>; 344*4882a593Smuzhiyun vmmc-supply = <&vmmcsd_fixed>; 345*4882a593Smuzhiyun bus-width = <8>; 346*4882a593Smuzhiyun non-removable; 347*4882a593Smuzhiyun status = "okay"; 348*4882a593Smuzhiyun}; 349*4882a593Smuzhiyun 350