1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ 4*4882a593Smuzhiyun * Copyright (C) 2018 Robert Bosch Power Tools GmbH 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include "am33xx.dtsi" 9*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 10*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun model = "Bosch AM335x Guardian"; 14*4882a593Smuzhiyun compatible = "bosch,am335x-guardian", "ti,am33xx"; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun chosen { 17*4882a593Smuzhiyun stdout-path = &uart0; 18*4882a593Smuzhiyun tick-timer = &timer2; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun cpus { 22*4882a593Smuzhiyun cpu@0 { 23*4882a593Smuzhiyun cpu0-supply = <&dcdc2_reg>; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun memory@80000000 { 28*4882a593Smuzhiyun device_type = "memory"; 29*4882a593Smuzhiyun reg = <0x80000000 0x10000000>; /* 256 MB */ 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun gpio_keys { 33*4882a593Smuzhiyun compatible = "gpio-keys"; 34*4882a593Smuzhiyun #address-cells = <1>; 35*4882a593Smuzhiyun #size-cells = <0>; 36*4882a593Smuzhiyun pinctrl-names = "default"; 37*4882a593Smuzhiyun pinctrl-0 = <&gpio_keys_pins>; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun button21 { 40*4882a593Smuzhiyun label = "guardian-power-button"; 41*4882a593Smuzhiyun linux,code = <KEY_POWER>; 42*4882a593Smuzhiyun gpios = <&gpio2 21 0>; 43*4882a593Smuzhiyun wakeup-source; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun leds { 48*4882a593Smuzhiyun compatible = "gpio-leds"; 49*4882a593Smuzhiyun pinctrl-names = "default"; 50*4882a593Smuzhiyun pinctrl-0 = <&leds_pins>; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun led1 { 53*4882a593Smuzhiyun label = "green:heartbeat"; 54*4882a593Smuzhiyun gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; 55*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 56*4882a593Smuzhiyun default-state = "off"; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun led2 { 60*4882a593Smuzhiyun label = "green:mmc0"; 61*4882a593Smuzhiyun gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 62*4882a593Smuzhiyun linux,default-trigger = "mmc0"; 63*4882a593Smuzhiyun default-state = "off"; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun panel { 68*4882a593Smuzhiyun compatible = "ti,tilcdc,panel"; 69*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 70*4882a593Smuzhiyun pinctrl-0 = <&lcd_pins_default &lcd_disen_pins>; 71*4882a593Smuzhiyun pinctrl-1 = <&lcd_pins_sleep>; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun display-timings { 74*4882a593Smuzhiyun 320x240 { 75*4882a593Smuzhiyun hactive = <320>; 76*4882a593Smuzhiyun vactive = <240>; 77*4882a593Smuzhiyun hback-porch = <68>; 78*4882a593Smuzhiyun hfront-porch = <20>; 79*4882a593Smuzhiyun hsync-len = <1>; 80*4882a593Smuzhiyun vback-porch = <18>; 81*4882a593Smuzhiyun vfront-porch = <4>; 82*4882a593Smuzhiyun vsync-len = <1>; 83*4882a593Smuzhiyun clock-frequency = <9000000>; 84*4882a593Smuzhiyun hsync-active = <0>; 85*4882a593Smuzhiyun vsync-active = <0>; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun panel-info { 89*4882a593Smuzhiyun ac-bias = <255>; 90*4882a593Smuzhiyun ac-bias-intrpt = <0>; 91*4882a593Smuzhiyun dma-burst-sz = <16>; 92*4882a593Smuzhiyun bpp = <24>; 93*4882a593Smuzhiyun bus-width = <16>; 94*4882a593Smuzhiyun fdd = <0x80>; 95*4882a593Smuzhiyun sync-edge = <0>; 96*4882a593Smuzhiyun sync-ctrl = <1>; 97*4882a593Smuzhiyun raster-order = <0>; 98*4882a593Smuzhiyun fifo-th = <0>; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun pwm7: dmtimer-pwm { 104*4882a593Smuzhiyun compatible = "ti,omap-dmtimer-pwm"; 105*4882a593Smuzhiyun ti,timers = <&timer7>; 106*4882a593Smuzhiyun pinctrl-names = "default"; 107*4882a593Smuzhiyun pinctrl-0 = <&dmtimer7_pins>; 108*4882a593Smuzhiyun ti,clock-source = <0x01>; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun vmmcsd_fixed: regulator-3v3 { 112*4882a593Smuzhiyun compatible = "regulator-fixed"; 113*4882a593Smuzhiyun regulator-name = "vmmcsd_fixed"; 114*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 115*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun}; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun&elm { 120*4882a593Smuzhiyun status = "okay"; 121*4882a593Smuzhiyun}; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun&gpmc { 124*4882a593Smuzhiyun pinctrl-names = "default"; 125*4882a593Smuzhiyun pinctrl-0 = <&nandflash_pins>; 126*4882a593Smuzhiyun ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ 127*4882a593Smuzhiyun status = "okay"; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun nand@0,0 { 130*4882a593Smuzhiyun compatible = "ti,omap2-nand"; 131*4882a593Smuzhiyun reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 132*4882a593Smuzhiyun interrupt-parent = <&gpmc>; 133*4882a593Smuzhiyun interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 134*4882a593Smuzhiyun <1 IRQ_TYPE_NONE>; /* termcount */ 135*4882a593Smuzhiyun rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ 136*4882a593Smuzhiyun ti,nand-ecc-opt = "bch16"; 137*4882a593Smuzhiyun ti,elm-id = <&elm>; 138*4882a593Smuzhiyun nand-bus-width = <8>; 139*4882a593Smuzhiyun gpmc,device-width = <1>; 140*4882a593Smuzhiyun gpmc,sync-clk-ps = <0>; 141*4882a593Smuzhiyun gpmc,cs-on-ns = <0>; 142*4882a593Smuzhiyun gpmc,cs-rd-off-ns = <44>; 143*4882a593Smuzhiyun gpmc,cs-wr-off-ns = <44>; 144*4882a593Smuzhiyun gpmc,adv-on-ns = <6>; 145*4882a593Smuzhiyun gpmc,adv-rd-off-ns = <34>; 146*4882a593Smuzhiyun gpmc,adv-wr-off-ns = <44>; 147*4882a593Smuzhiyun gpmc,we-on-ns = <0>; 148*4882a593Smuzhiyun gpmc,we-off-ns = <40>; 149*4882a593Smuzhiyun gpmc,oe-on-ns = <0>; 150*4882a593Smuzhiyun gpmc,oe-off-ns = <54>; 151*4882a593Smuzhiyun gpmc,access-ns = <64>; 152*4882a593Smuzhiyun gpmc,rd-cycle-ns = <82>; 153*4882a593Smuzhiyun gpmc,wr-cycle-ns = <82>; 154*4882a593Smuzhiyun gpmc,bus-turnaround-ns = <0>; 155*4882a593Smuzhiyun gpmc,cycle2cycle-delay-ns = <0>; 156*4882a593Smuzhiyun gpmc,clk-activation-ns = <0>; 157*4882a593Smuzhiyun gpmc,wr-access-ns = <40>; 158*4882a593Smuzhiyun gpmc,wr-data-mux-bus-ns = <0>; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun /* 161*4882a593Smuzhiyun * MTD partition table 162*4882a593Smuzhiyun * 163*4882a593Smuzhiyun * All SPL-* partitions are sized to minimal length which can 164*4882a593Smuzhiyun * be independently programmable. For NAND flash this is equal 165*4882a593Smuzhiyun * to size of erase-block. 166*4882a593Smuzhiyun */ 167*4882a593Smuzhiyun #address-cells = <1>; 168*4882a593Smuzhiyun #size-cells = <1>; 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun partition@0 { 171*4882a593Smuzhiyun label = "SPL"; 172*4882a593Smuzhiyun reg = <0x0 0x40000>; 173*4882a593Smuzhiyun }; 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun partition@1 { 176*4882a593Smuzhiyun label = "SPL.backup1"; 177*4882a593Smuzhiyun reg = <0x40000 0x40000>; 178*4882a593Smuzhiyun }; 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun partition@2 { 181*4882a593Smuzhiyun label = "SPL.backup2"; 182*4882a593Smuzhiyun reg = <0x80000 0x40000>; 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun partition@3 { 186*4882a593Smuzhiyun label = "SPL.backup3"; 187*4882a593Smuzhiyun reg = <0xc0000 0x40000>; 188*4882a593Smuzhiyun }; 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun partition@4 { 191*4882a593Smuzhiyun label = "u-boot"; 192*4882a593Smuzhiyun reg = <0x100000 0x100000>; 193*4882a593Smuzhiyun }; 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun partition@5 { 196*4882a593Smuzhiyun label = "u-boot.backup1"; 197*4882a593Smuzhiyun reg = <0x200000 0x100000>; 198*4882a593Smuzhiyun }; 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun partition@6 { 201*4882a593Smuzhiyun label = "u-boot-env"; 202*4882a593Smuzhiyun reg = <0x300000 0x40000>; 203*4882a593Smuzhiyun }; 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun partition@7 { 206*4882a593Smuzhiyun label = "u-boot-env.backup1"; 207*4882a593Smuzhiyun reg = <0x340000 0x40000>; 208*4882a593Smuzhiyun }; 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun partition@8 { 211*4882a593Smuzhiyun label = "UBI"; 212*4882a593Smuzhiyun reg = <0x380000 0x1fc80000>; 213*4882a593Smuzhiyun }; 214*4882a593Smuzhiyun }; 215*4882a593Smuzhiyun}; 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun&i2c0 { 218*4882a593Smuzhiyun pinctrl-names = "default"; 219*4882a593Smuzhiyun pinctrl-0 = <&i2c0_pins>; 220*4882a593Smuzhiyun clock-frequency = <400000>; 221*4882a593Smuzhiyun status = "okay"; 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun tps: tps@24 { 224*4882a593Smuzhiyun reg = <0x24>; 225*4882a593Smuzhiyun }; 226*4882a593Smuzhiyun}; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun&lcdc { 229*4882a593Smuzhiyun blue-and-red-wiring = "crossed"; 230*4882a593Smuzhiyun status = "okay"; 231*4882a593Smuzhiyun}; 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun&mmc1 { 234*4882a593Smuzhiyun bus-width = <0x4>; 235*4882a593Smuzhiyun pinctrl-names = "default"; 236*4882a593Smuzhiyun pinctrl-0 = <&mmc1_pins>; 237*4882a593Smuzhiyun cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; 238*4882a593Smuzhiyun vmmc-supply = <&vmmcsd_fixed>; 239*4882a593Smuzhiyun status = "okay"; 240*4882a593Smuzhiyun}; 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun&rtc { 243*4882a593Smuzhiyun clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; 244*4882a593Smuzhiyun clock-names = "ext-clk", "int-clk"; 245*4882a593Smuzhiyun system-power-controller; 246*4882a593Smuzhiyun}; 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun&spi0 { 249*4882a593Smuzhiyun ti,pindir-d0-out-d1-in; 250*4882a593Smuzhiyun pinctrl-names = "default"; 251*4882a593Smuzhiyun pinctrl-0 = <&spi0_pins>; 252*4882a593Smuzhiyun status = "okay"; 253*4882a593Smuzhiyun}; 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun#include "tps65217.dtsi" 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun&tps { 258*4882a593Smuzhiyun ti,pmic-shutdown-controller; 259*4882a593Smuzhiyun interrupt-parent = <&intc>; 260*4882a593Smuzhiyun interrupts = <7>; /* NMI */ 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun backlight { 263*4882a593Smuzhiyun isel = <1>; /* 1 - ISET1, 2 ISET2 */ 264*4882a593Smuzhiyun fdim = <100>; /* TPS65217_BL_FDIM_100HZ */ 265*4882a593Smuzhiyun default-brightness = <100>; 266*4882a593Smuzhiyun }; 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun regulators { 269*4882a593Smuzhiyun dcdc1_reg: regulator@0 { 270*4882a593Smuzhiyun regulator-name = "vdds_dpr"; 271*4882a593Smuzhiyun regulator-always-on; 272*4882a593Smuzhiyun }; 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun dcdc2_reg: regulator@1 { 275*4882a593Smuzhiyun regulator-name = "vdd_mpu"; 276*4882a593Smuzhiyun regulator-min-microvolt = <925000>; 277*4882a593Smuzhiyun regulator-max-microvolt = <1351500>; 278*4882a593Smuzhiyun regulator-boot-on; 279*4882a593Smuzhiyun regulator-always-on; 280*4882a593Smuzhiyun }; 281*4882a593Smuzhiyun 282*4882a593Smuzhiyun dcdc3_reg: regulator@2 { 283*4882a593Smuzhiyun regulator-name = "vdd_core"; 284*4882a593Smuzhiyun regulator-min-microvolt = <925000>; 285*4882a593Smuzhiyun regulator-max-microvolt = <1150000>; 286*4882a593Smuzhiyun regulator-boot-on; 287*4882a593Smuzhiyun regulator-always-on; 288*4882a593Smuzhiyun }; 289*4882a593Smuzhiyun 290*4882a593Smuzhiyun ldo1_reg: regulator@3 { 291*4882a593Smuzhiyun regulator-name = "vio,vrtc,vdds"; 292*4882a593Smuzhiyun regulator-always-on; 293*4882a593Smuzhiyun }; 294*4882a593Smuzhiyun 295*4882a593Smuzhiyun ldo2_reg: regulator@4 { 296*4882a593Smuzhiyun regulator-name = "vdd_3v3aux"; 297*4882a593Smuzhiyun regulator-always-on; 298*4882a593Smuzhiyun }; 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun ldo3_reg: regulator@5 { 301*4882a593Smuzhiyun regulator-name = "vdd_1v8"; 302*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 303*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 304*4882a593Smuzhiyun regulator-always-on; 305*4882a593Smuzhiyun }; 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun ldo4_reg: regulator@6 { 308*4882a593Smuzhiyun regulator-name = "vdd_3v3a"; 309*4882a593Smuzhiyun regulator-always-on; 310*4882a593Smuzhiyun }; 311*4882a593Smuzhiyun }; 312*4882a593Smuzhiyun}; 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun&tscadc { 315*4882a593Smuzhiyun status = "okay"; 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun adc { 318*4882a593Smuzhiyun ti,adc-channels = <0 1 2 3 4 5 6>; 319*4882a593Smuzhiyun }; 320*4882a593Smuzhiyun}; 321*4882a593Smuzhiyun 322*4882a593Smuzhiyun&uart0 { 323*4882a593Smuzhiyun pinctrl-names = "default"; 324*4882a593Smuzhiyun pinctrl-0 = <&uart0_pins>; 325*4882a593Smuzhiyun status = "okay"; 326*4882a593Smuzhiyun}; 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun&usb0 { 329*4882a593Smuzhiyun dr_mode = "peripheral"; 330*4882a593Smuzhiyun}; 331*4882a593Smuzhiyun 332*4882a593Smuzhiyun&usb1 { 333*4882a593Smuzhiyun dr_mode = "host"; 334*4882a593Smuzhiyun}; 335*4882a593Smuzhiyun 336*4882a593Smuzhiyun&am33xx_pinmux { 337*4882a593Smuzhiyun pinctrl-names = "default"; 338*4882a593Smuzhiyun pinctrl-0 = <&clkout2_pin &gpio_pins>; 339*4882a593Smuzhiyun 340*4882a593Smuzhiyun clkout2_pin: pinmux_clkout2_pin { 341*4882a593Smuzhiyun pinctrl-single,pins = < 342*4882a593Smuzhiyun AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) 343*4882a593Smuzhiyun >; 344*4882a593Smuzhiyun }; 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun dmtimer7_pins: pinmux_dmtimer7_pins { 347*4882a593Smuzhiyun pinctrl-single,pins = < 348*4882a593Smuzhiyun AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE5) 349*4882a593Smuzhiyun >; 350*4882a593Smuzhiyun }; 351*4882a593Smuzhiyun 352*4882a593Smuzhiyun gpio_keys_pins: pinmux_gpio_keys_pins { 353*4882a593Smuzhiyun pinctrl-single,pins = < 354*4882a593Smuzhiyun AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE7) 355*4882a593Smuzhiyun >; 356*4882a593Smuzhiyun }; 357*4882a593Smuzhiyun 358*4882a593Smuzhiyun gpio_pins: pinmux_gpio_pins { 359*4882a593Smuzhiyun pinctrl-single,pins = < 360*4882a593Smuzhiyun AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE7) 361*4882a593Smuzhiyun AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE7) 362*4882a593Smuzhiyun >; 363*4882a593Smuzhiyun }; 364*4882a593Smuzhiyun 365*4882a593Smuzhiyun i2c0_pins: pinmux_i2c0_pins { 366*4882a593Smuzhiyun pinctrl-single,pins = < 367*4882a593Smuzhiyun AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) 368*4882a593Smuzhiyun AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) 369*4882a593Smuzhiyun >; 370*4882a593Smuzhiyun }; 371*4882a593Smuzhiyun 372*4882a593Smuzhiyun lcd_disen_pins: pinmux_lcd_disen_pins { 373*4882a593Smuzhiyun pinctrl-single,pins = < 374*4882a593Smuzhiyun AM33XX_IOPAD(0x9a4, PIN_OUTPUT_PULLUP | SLEWCTRL_SLOW | MUX_MODE7) 375*4882a593Smuzhiyun >; 376*4882a593Smuzhiyun }; 377*4882a593Smuzhiyun 378*4882a593Smuzhiyun lcd_pins_default: pinmux_lcd_pins_default { 379*4882a593Smuzhiyun pinctrl-single,pins = < 380*4882a593Smuzhiyun AM33XX_IOPAD(0x820, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) 381*4882a593Smuzhiyun AM33XX_IOPAD(0x824, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) 382*4882a593Smuzhiyun AM33XX_IOPAD(0x828, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) 383*4882a593Smuzhiyun AM33XX_IOPAD(0x82c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) 384*4882a593Smuzhiyun AM33XX_IOPAD(0x830, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) 385*4882a593Smuzhiyun AM33XX_IOPAD(0x834, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) 386*4882a593Smuzhiyun AM33XX_IOPAD(0x838, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) 387*4882a593Smuzhiyun AM33XX_IOPAD(0x83c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) 388*4882a593Smuzhiyun AM33XX_IOPAD(0x8a0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 389*4882a593Smuzhiyun AM33XX_IOPAD(0x8a4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 390*4882a593Smuzhiyun AM33XX_IOPAD(0x8a8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 391*4882a593Smuzhiyun AM33XX_IOPAD(0x8ac, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 392*4882a593Smuzhiyun AM33XX_IOPAD(0x8b0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 393*4882a593Smuzhiyun AM33XX_IOPAD(0x8b4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 394*4882a593Smuzhiyun AM33XX_IOPAD(0x8b8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 395*4882a593Smuzhiyun AM33XX_IOPAD(0x8bc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 396*4882a593Smuzhiyun AM33XX_IOPAD(0x8c0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 397*4882a593Smuzhiyun AM33XX_IOPAD(0x8c4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 398*4882a593Smuzhiyun AM33XX_IOPAD(0x8c8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 399*4882a593Smuzhiyun AM33XX_IOPAD(0x8cc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 400*4882a593Smuzhiyun AM33XX_IOPAD(0x8d0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 401*4882a593Smuzhiyun AM33XX_IOPAD(0x8d4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 402*4882a593Smuzhiyun AM33XX_IOPAD(0x8d8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 403*4882a593Smuzhiyun AM33XX_IOPAD(0x8dc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 404*4882a593Smuzhiyun AM33XX_IOPAD(0x8e0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 405*4882a593Smuzhiyun AM33XX_IOPAD(0x8e4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 406*4882a593Smuzhiyun AM33XX_IOPAD(0x8e8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 407*4882a593Smuzhiyun AM33XX_IOPAD(0x8ec, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) 408*4882a593Smuzhiyun >; 409*4882a593Smuzhiyun }; 410*4882a593Smuzhiyun 411*4882a593Smuzhiyun lcd_pins_sleep: pinmux_lcd_pins_sleep { 412*4882a593Smuzhiyun pinctrl-single,pins = < 413*4882a593Smuzhiyun AM33XX_IOPAD(0x8a0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) 414*4882a593Smuzhiyun AM33XX_IOPAD(0x8a4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) 415*4882a593Smuzhiyun AM33XX_IOPAD(0x8a8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) 416*4882a593Smuzhiyun AM33XX_IOPAD(0x8ac, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) 417*4882a593Smuzhiyun AM33XX_IOPAD(0x8b0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) 418*4882a593Smuzhiyun AM33XX_IOPAD(0x8b4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) 419*4882a593Smuzhiyun AM33XX_IOPAD(0x8b8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) 420*4882a593Smuzhiyun AM33XX_IOPAD(0x8bc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) 421*4882a593Smuzhiyun AM33XX_IOPAD(0x8c0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) 422*4882a593Smuzhiyun AM33XX_IOPAD(0x8c4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) 423*4882a593Smuzhiyun AM33XX_IOPAD(0x8c8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) 424*4882a593Smuzhiyun AM33XX_IOPAD(0x8cc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) 425*4882a593Smuzhiyun AM33XX_IOPAD(0x8d0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) 426*4882a593Smuzhiyun AM33XX_IOPAD(0x8d4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) 427*4882a593Smuzhiyun AM33XX_IOPAD(0x8d8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) 428*4882a593Smuzhiyun AM33XX_IOPAD(0x8dc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) 429*4882a593Smuzhiyun AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) 430*4882a593Smuzhiyun AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) 431*4882a593Smuzhiyun AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) 432*4882a593Smuzhiyun AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) 433*4882a593Smuzhiyun >; 434*4882a593Smuzhiyun }; 435*4882a593Smuzhiyun 436*4882a593Smuzhiyun leds_pins: pinmux_leds_pins { 437*4882a593Smuzhiyun pinctrl-single,pins = < 438*4882a593Smuzhiyun AM33XX_IOPAD(0x868, PIN_OUTPUT | MUX_MODE7) 439*4882a593Smuzhiyun AM33XX_IOPAD(0x86c, PIN_OUTPUT | MUX_MODE7) 440*4882a593Smuzhiyun >; 441*4882a593Smuzhiyun }; 442*4882a593Smuzhiyun 443*4882a593Smuzhiyun mmc1_pins: pinmux_mmc1_pins { 444*4882a593Smuzhiyun pinctrl-single,pins = < 445*4882a593Smuzhiyun AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) 446*4882a593Smuzhiyun AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) 447*4882a593Smuzhiyun AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) 448*4882a593Smuzhiyun AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) 449*4882a593Smuzhiyun AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) 450*4882a593Smuzhiyun AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) 451*4882a593Smuzhiyun AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) 452*4882a593Smuzhiyun >; 453*4882a593Smuzhiyun }; 454*4882a593Smuzhiyun 455*4882a593Smuzhiyun spi0_pins: pinmux_spi0_pins { 456*4882a593Smuzhiyun pinctrl-single,pins = < 457*4882a593Smuzhiyun AM33XX_IOPAD(0x950, PIN_OUTPUT_PULLDOWN | MUX_MODE0) 458*4882a593Smuzhiyun AM33XX_IOPAD(0x954, PIN_OUTPUT_PULLUP | MUX_MODE0) 459*4882a593Smuzhiyun AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) 460*4882a593Smuzhiyun AM33XX_IOPAD(0x95c, PIN_OUTPUT_PULLUP | MUX_MODE0) 461*4882a593Smuzhiyun >; 462*4882a593Smuzhiyun }; 463*4882a593Smuzhiyun 464*4882a593Smuzhiyun uart0_pins: pinmux_uart0_pins { 465*4882a593Smuzhiyun pinctrl-single,pins = < 466*4882a593Smuzhiyun AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) 467*4882a593Smuzhiyun AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) 468*4882a593Smuzhiyun >; 469*4882a593Smuzhiyun }; 470*4882a593Smuzhiyun 471*4882a593Smuzhiyun nandflash_pins: pinmux_nandflash_pins { 472*4882a593Smuzhiyun pinctrl-single,pins = < 473*4882a593Smuzhiyun AM33XX_IOPAD(0x800, PIN_INPUT | MUX_MODE0) 474*4882a593Smuzhiyun AM33XX_IOPAD(0x804, PIN_INPUT | MUX_MODE0) 475*4882a593Smuzhiyun AM33XX_IOPAD(0x808, PIN_INPUT | MUX_MODE0) 476*4882a593Smuzhiyun AM33XX_IOPAD(0x80c, PIN_INPUT | MUX_MODE0) 477*4882a593Smuzhiyun AM33XX_IOPAD(0x810, PIN_INPUT | MUX_MODE0) 478*4882a593Smuzhiyun AM33XX_IOPAD(0x814, PIN_INPUT | MUX_MODE0) 479*4882a593Smuzhiyun AM33XX_IOPAD(0x818, PIN_INPUT | MUX_MODE0) 480*4882a593Smuzhiyun AM33XX_IOPAD(0x81c, PIN_INPUT | MUX_MODE0) 481*4882a593Smuzhiyun AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE0) 482*4882a593Smuzhiyun AM33XX_IOPAD(0x874, PIN_OUTPUT | MUX_MODE0) 483*4882a593Smuzhiyun AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) 484*4882a593Smuzhiyun AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) 485*4882a593Smuzhiyun AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) 486*4882a593Smuzhiyun AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) 487*4882a593Smuzhiyun AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) 488*4882a593Smuzhiyun >; 489*4882a593Smuzhiyun }; 490*4882a593Smuzhiyun}; 491