1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun#include <dt-bindings/display/tda998x.h> 7*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h> 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun&ldo3_reg { 10*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 11*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 12*4882a593Smuzhiyun regulator-always-on; 13*4882a593Smuzhiyun}; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun&mmc1 { 16*4882a593Smuzhiyun vmmc-supply = <&vmmcsd_fixed>; 17*4882a593Smuzhiyun}; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun&mmc2 { 20*4882a593Smuzhiyun vmmc-supply = <&vmmcsd_fixed>; 21*4882a593Smuzhiyun pinctrl-names = "default"; 22*4882a593Smuzhiyun pinctrl-0 = <&emmc_pins>; 23*4882a593Smuzhiyun bus-width = <8>; 24*4882a593Smuzhiyun status = "okay"; 25*4882a593Smuzhiyun non-removable; 26*4882a593Smuzhiyun}; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun&am33xx_pinmux { 29*4882a593Smuzhiyun nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins { 30*4882a593Smuzhiyun pinctrl-single,pins = < 31*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) 32*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) 33*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) 34*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) 35*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) 36*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) 37*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) 38*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) 39*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) 40*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) 41*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) 42*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) 43*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) 44*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) 45*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) 46*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) 47*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) 48*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 49*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 50*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 51*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 52*4882a593Smuzhiyun >; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins { 56*4882a593Smuzhiyun pinctrl-single,pins = < 57*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) 58*4882a593Smuzhiyun >; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun mcasp0_pins: mcasp0_pins { 62*4882a593Smuzhiyun pinctrl-single,pins = < 63*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */ 64*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/ 65*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0) 66*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 67*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */ 68*4882a593Smuzhiyun >; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun}; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun&lcdc { 73*4882a593Smuzhiyun status = "okay"; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* If you want to get 24 bit RGB and 16 BGR mode instead of 76*4882a593Smuzhiyun * current 16 bit RGB and 24 BGR modes, set the propety 77*4882a593Smuzhiyun * below to "crossed" and uncomment the video-ports -property 78*4882a593Smuzhiyun * in tda19988 node. 79*4882a593Smuzhiyun */ 80*4882a593Smuzhiyun blue-and-red-wiring = "straight"; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun port { 83*4882a593Smuzhiyun lcdc_0: endpoint@0 { 84*4882a593Smuzhiyun remote-endpoint = <&hdmi_0>; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun}; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun&i2c0 { 90*4882a593Smuzhiyun tda19988: tda19988@70 { 91*4882a593Smuzhiyun compatible = "nxp,tda998x"; 92*4882a593Smuzhiyun reg = <0x70>; 93*4882a593Smuzhiyun nxp,calib-gpios = <&gpio1 25 0>; 94*4882a593Smuzhiyun interrupts-extended = <&gpio1 25 IRQ_TYPE_LEVEL_LOW>; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun pinctrl-names = "default", "off"; 97*4882a593Smuzhiyun pinctrl-0 = <&nxp_hdmi_bonelt_pins>; 98*4882a593Smuzhiyun pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* Convert 24bit BGR to RGB, e.g. cross red and blue wiring */ 101*4882a593Smuzhiyun /* video-ports = <0x234501>; */ 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #sound-dai-cells = <0>; 104*4882a593Smuzhiyun audio-ports = < TDA998x_I2S 0x03>; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun ports { 107*4882a593Smuzhiyun port@0 { 108*4882a593Smuzhiyun hdmi_0: endpoint@0 { 109*4882a593Smuzhiyun remote-endpoint = <&lcdc_0>; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun}; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun&rtc { 117*4882a593Smuzhiyun system-power-controller; 118*4882a593Smuzhiyun}; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun&mcasp0 { 121*4882a593Smuzhiyun #sound-dai-cells = <0>; 122*4882a593Smuzhiyun pinctrl-names = "default"; 123*4882a593Smuzhiyun pinctrl-0 = <&mcasp0_pins>; 124*4882a593Smuzhiyun status = "okay"; 125*4882a593Smuzhiyun op-mode = <0>; /* MCASP_IIS_MODE */ 126*4882a593Smuzhiyun tdm-slots = <2>; 127*4882a593Smuzhiyun serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 128*4882a593Smuzhiyun 0 0 1 0 129*4882a593Smuzhiyun >; 130*4882a593Smuzhiyun tx-num-evt = <32>; 131*4882a593Smuzhiyun rx-num-evt = <32>; 132*4882a593Smuzhiyun}; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun/ { 135*4882a593Smuzhiyun memory@80000000 { 136*4882a593Smuzhiyun device_type = "memory"; 137*4882a593Smuzhiyun reg = <0x80000000 0x20000000>; /* 512 MB */ 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun clk_mcasp0_fixed: clk_mcasp0_fixed { 141*4882a593Smuzhiyun #clock-cells = <0>; 142*4882a593Smuzhiyun compatible = "fixed-clock"; 143*4882a593Smuzhiyun clock-frequency = <24576000>; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun clk_mcasp0: clk_mcasp0 { 147*4882a593Smuzhiyun #clock-cells = <0>; 148*4882a593Smuzhiyun compatible = "gpio-gate-clock"; 149*4882a593Smuzhiyun clocks = <&clk_mcasp0_fixed>; 150*4882a593Smuzhiyun enable-gpios = <&gpio1 27 0>; /* BeagleBone Black Clk enable on GPIO1_27 */ 151*4882a593Smuzhiyun }; 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun sound { 154*4882a593Smuzhiyun compatible = "simple-audio-card"; 155*4882a593Smuzhiyun simple-audio-card,name = "TI BeagleBone Black"; 156*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 157*4882a593Smuzhiyun simple-audio-card,bitclock-master = <&dailink0_master>; 158*4882a593Smuzhiyun simple-audio-card,frame-master = <&dailink0_master>; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun dailink0_master: simple-audio-card,cpu { 161*4882a593Smuzhiyun sound-dai = <&mcasp0>; 162*4882a593Smuzhiyun clocks = <&clk_mcasp0>; 163*4882a593Smuzhiyun }; 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun simple-audio-card,codec { 166*4882a593Smuzhiyun sound-dai = <&tda19988>; 167*4882a593Smuzhiyun }; 168*4882a593Smuzhiyun }; 169*4882a593Smuzhiyun}; 170