1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/ { 7*4882a593Smuzhiyun cpus { 8*4882a593Smuzhiyun cpu@0 { 9*4882a593Smuzhiyun cpu0-supply = <&dcdc2_reg>; 10*4882a593Smuzhiyun }; 11*4882a593Smuzhiyun }; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun memory@80000000 { 14*4882a593Smuzhiyun device_type = "memory"; 15*4882a593Smuzhiyun reg = <0x80000000 0x10000000>; /* 256 MB */ 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun chosen { 19*4882a593Smuzhiyun stdout-path = &uart0; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun leds { 23*4882a593Smuzhiyun pinctrl-names = "default"; 24*4882a593Smuzhiyun pinctrl-0 = <&user_leds_s0>; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun compatible = "gpio-leds"; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun led2 { 29*4882a593Smuzhiyun label = "beaglebone:green:heartbeat"; 30*4882a593Smuzhiyun gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; 31*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 32*4882a593Smuzhiyun default-state = "off"; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun led3 { 36*4882a593Smuzhiyun label = "beaglebone:green:mmc0"; 37*4882a593Smuzhiyun gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; 38*4882a593Smuzhiyun linux,default-trigger = "mmc0"; 39*4882a593Smuzhiyun default-state = "off"; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun led4 { 43*4882a593Smuzhiyun label = "beaglebone:green:usr2"; 44*4882a593Smuzhiyun gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; 45*4882a593Smuzhiyun linux,default-trigger = "cpu0"; 46*4882a593Smuzhiyun default-state = "off"; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun led5 { 50*4882a593Smuzhiyun label = "beaglebone:green:usr3"; 51*4882a593Smuzhiyun gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; 52*4882a593Smuzhiyun linux,default-trigger = "mmc1"; 53*4882a593Smuzhiyun default-state = "off"; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun vmmcsd_fixed: fixedregulator0 { 58*4882a593Smuzhiyun compatible = "regulator-fixed"; 59*4882a593Smuzhiyun regulator-name = "vmmcsd_fixed"; 60*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 61*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun}; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun&am33xx_pinmux { 66*4882a593Smuzhiyun pinctrl-names = "default"; 67*4882a593Smuzhiyun pinctrl-0 = <&clkout2_pin>; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun user_leds_s0: user_leds_s0 { 70*4882a593Smuzhiyun pinctrl-single,pins = < 71*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ 72*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a6.gpio1_22 */ 73*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a7.gpio1_23 */ 74*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a8.gpio1_24 */ 75*4882a593Smuzhiyun >; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun i2c0_pins: pinmux_i2c0_pins { 79*4882a593Smuzhiyun pinctrl-single,pins = < 80*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_sda.i2c0_sda */ 81*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_scl.i2c0_scl */ 82*4882a593Smuzhiyun >; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun i2c2_pins: pinmux_i2c2_pins { 86*4882a593Smuzhiyun pinctrl-single,pins = < 87*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_ctsn.i2c2_sda */ 88*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_rtsn.i2c2_scl */ 89*4882a593Smuzhiyun >; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun uart0_pins: pinmux_uart0_pins { 93*4882a593Smuzhiyun pinctrl-single,pins = < 94*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) 95*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 96*4882a593Smuzhiyun >; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun clkout2_pin: pinmux_clkout2_pin { 100*4882a593Smuzhiyun pinctrl-single,pins = < 101*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ 102*4882a593Smuzhiyun >; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun cpsw_default: cpsw_default { 106*4882a593Smuzhiyun pinctrl-single,pins = < 107*4882a593Smuzhiyun /* Slave 1 */ 108*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0) 109*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 110*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE0) 111*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 112*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 113*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 114*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 115*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) 116*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) 117*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE0) 118*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE0) 119*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE0) 120*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE0) 121*4882a593Smuzhiyun >; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun cpsw_sleep: cpsw_sleep { 125*4882a593Smuzhiyun pinctrl-single,pins = < 126*4882a593Smuzhiyun /* Slave 1 reset value */ 127*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) 128*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) 129*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) 130*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) 131*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) 132*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) 133*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) 134*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) 135*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) 136*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) 137*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) 138*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) 139*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) 140*4882a593Smuzhiyun >; 141*4882a593Smuzhiyun }; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun davinci_mdio_default: davinci_mdio_default { 144*4882a593Smuzhiyun pinctrl-single,pins = < 145*4882a593Smuzhiyun /* MDIO */ 146*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) 147*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) 148*4882a593Smuzhiyun >; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun davinci_mdio_sleep: davinci_mdio_sleep { 152*4882a593Smuzhiyun pinctrl-single,pins = < 153*4882a593Smuzhiyun /* MDIO reset value */ 154*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) 155*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) 156*4882a593Smuzhiyun >; 157*4882a593Smuzhiyun }; 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun mmc1_pins: pinmux_mmc1_pins { 160*4882a593Smuzhiyun pinctrl-single,pins = < 161*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spio0_cs1.gpio0_6 */ 162*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) 163*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) 164*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) 165*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) 166*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) 167*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) 168*4882a593Smuzhiyun >; 169*4882a593Smuzhiyun }; 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun emmc_pins: pinmux_emmc_pins { 172*4882a593Smuzhiyun pinctrl-single,pins = < 173*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ 174*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ 175*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ 176*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ 177*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ 178*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ 179*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ 180*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ 181*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ 182*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ 183*4882a593Smuzhiyun >; 184*4882a593Smuzhiyun }; 185*4882a593Smuzhiyun}; 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun&uart0 { 188*4882a593Smuzhiyun pinctrl-names = "default"; 189*4882a593Smuzhiyun pinctrl-0 = <&uart0_pins>; 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun status = "okay"; 192*4882a593Smuzhiyun}; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun&usb0 { 195*4882a593Smuzhiyun dr_mode = "peripheral"; 196*4882a593Smuzhiyun interrupts-extended = <&intc 18 &tps 0>; 197*4882a593Smuzhiyun interrupt-names = "mc", "vbus"; 198*4882a593Smuzhiyun}; 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun&usb1 { 201*4882a593Smuzhiyun dr_mode = "host"; 202*4882a593Smuzhiyun}; 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun&i2c0 { 205*4882a593Smuzhiyun pinctrl-names = "default"; 206*4882a593Smuzhiyun pinctrl-0 = <&i2c0_pins>; 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun status = "okay"; 209*4882a593Smuzhiyun clock-frequency = <400000>; 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun tps: tps@24 { 212*4882a593Smuzhiyun reg = <0x24>; 213*4882a593Smuzhiyun }; 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun baseboard_eeprom: baseboard_eeprom@50 { 216*4882a593Smuzhiyun compatible = "atmel,24c256"; 217*4882a593Smuzhiyun reg = <0x50>; 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun #address-cells = <1>; 220*4882a593Smuzhiyun #size-cells = <1>; 221*4882a593Smuzhiyun baseboard_data: baseboard_data@0 { 222*4882a593Smuzhiyun reg = <0 0x100>; 223*4882a593Smuzhiyun }; 224*4882a593Smuzhiyun }; 225*4882a593Smuzhiyun}; 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun&i2c2 { 228*4882a593Smuzhiyun pinctrl-names = "default"; 229*4882a593Smuzhiyun pinctrl-0 = <&i2c2_pins>; 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun status = "okay"; 232*4882a593Smuzhiyun clock-frequency = <100000>; 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun cape_eeprom0: cape_eeprom0@54 { 235*4882a593Smuzhiyun compatible = "atmel,24c256"; 236*4882a593Smuzhiyun reg = <0x54>; 237*4882a593Smuzhiyun #address-cells = <1>; 238*4882a593Smuzhiyun #size-cells = <1>; 239*4882a593Smuzhiyun cape0_data: cape_data@0 { 240*4882a593Smuzhiyun reg = <0 0x100>; 241*4882a593Smuzhiyun }; 242*4882a593Smuzhiyun }; 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun cape_eeprom1: cape_eeprom1@55 { 245*4882a593Smuzhiyun compatible = "atmel,24c256"; 246*4882a593Smuzhiyun reg = <0x55>; 247*4882a593Smuzhiyun #address-cells = <1>; 248*4882a593Smuzhiyun #size-cells = <1>; 249*4882a593Smuzhiyun cape1_data: cape_data@0 { 250*4882a593Smuzhiyun reg = <0 0x100>; 251*4882a593Smuzhiyun }; 252*4882a593Smuzhiyun }; 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun cape_eeprom2: cape_eeprom2@56 { 255*4882a593Smuzhiyun compatible = "atmel,24c256"; 256*4882a593Smuzhiyun reg = <0x56>; 257*4882a593Smuzhiyun #address-cells = <1>; 258*4882a593Smuzhiyun #size-cells = <1>; 259*4882a593Smuzhiyun cape2_data: cape_data@0 { 260*4882a593Smuzhiyun reg = <0 0x100>; 261*4882a593Smuzhiyun }; 262*4882a593Smuzhiyun }; 263*4882a593Smuzhiyun 264*4882a593Smuzhiyun cape_eeprom3: cape_eeprom3@57 { 265*4882a593Smuzhiyun compatible = "atmel,24c256"; 266*4882a593Smuzhiyun reg = <0x57>; 267*4882a593Smuzhiyun #address-cells = <1>; 268*4882a593Smuzhiyun #size-cells = <1>; 269*4882a593Smuzhiyun cape3_data: cape_data@0 { 270*4882a593Smuzhiyun reg = <0 0x100>; 271*4882a593Smuzhiyun }; 272*4882a593Smuzhiyun }; 273*4882a593Smuzhiyun}; 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun/include/ "tps65217.dtsi" 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun&tps { 279*4882a593Smuzhiyun /* 280*4882a593Smuzhiyun * Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only 281*4882a593Smuzhiyun * mode") at poweroff. Most BeagleBone versions do not support RTC-only 282*4882a593Smuzhiyun * mode and risk hardware damage if this mode is entered. 283*4882a593Smuzhiyun * 284*4882a593Smuzhiyun * For details, see linux-omap mailing list May 2015 thread 285*4882a593Smuzhiyun * [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller 286*4882a593Smuzhiyun * In particular, messages: 287*4882a593Smuzhiyun * http://www.spinics.net/lists/linux-omap/msg118585.html 288*4882a593Smuzhiyun * http://www.spinics.net/lists/linux-omap/msg118615.html 289*4882a593Smuzhiyun * 290*4882a593Smuzhiyun * You can override this later with 291*4882a593Smuzhiyun * &tps { /delete-property/ ti,pmic-shutdown-controller; } 292*4882a593Smuzhiyun * if you want to use RTC-only mode and made sure you are not affected 293*4882a593Smuzhiyun * by the hardware problems. (Tip: double-check by performing a current 294*4882a593Smuzhiyun * measurement after shutdown: it should be less than 1 mA.) 295*4882a593Smuzhiyun */ 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun interrupts = <7>; /* NMI */ 298*4882a593Smuzhiyun interrupt-parent = <&intc>; 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun ti,pmic-shutdown-controller; 301*4882a593Smuzhiyun 302*4882a593Smuzhiyun charger { 303*4882a593Smuzhiyun status = "okay"; 304*4882a593Smuzhiyun }; 305*4882a593Smuzhiyun 306*4882a593Smuzhiyun pwrbutton { 307*4882a593Smuzhiyun status = "okay"; 308*4882a593Smuzhiyun }; 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun regulators { 311*4882a593Smuzhiyun dcdc1_reg: regulator@0 { 312*4882a593Smuzhiyun regulator-name = "vdds_dpr"; 313*4882a593Smuzhiyun regulator-always-on; 314*4882a593Smuzhiyun }; 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun dcdc2_reg: regulator@1 { 317*4882a593Smuzhiyun /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ 318*4882a593Smuzhiyun regulator-name = "vdd_mpu"; 319*4882a593Smuzhiyun regulator-min-microvolt = <925000>; 320*4882a593Smuzhiyun regulator-max-microvolt = <1351500>; 321*4882a593Smuzhiyun regulator-boot-on; 322*4882a593Smuzhiyun regulator-always-on; 323*4882a593Smuzhiyun }; 324*4882a593Smuzhiyun 325*4882a593Smuzhiyun dcdc3_reg: regulator@2 { 326*4882a593Smuzhiyun /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ 327*4882a593Smuzhiyun regulator-name = "vdd_core"; 328*4882a593Smuzhiyun regulator-min-microvolt = <925000>; 329*4882a593Smuzhiyun regulator-max-microvolt = <1150000>; 330*4882a593Smuzhiyun regulator-boot-on; 331*4882a593Smuzhiyun regulator-always-on; 332*4882a593Smuzhiyun }; 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun ldo1_reg: regulator@3 { 335*4882a593Smuzhiyun regulator-name = "vio,vrtc,vdds"; 336*4882a593Smuzhiyun regulator-always-on; 337*4882a593Smuzhiyun }; 338*4882a593Smuzhiyun 339*4882a593Smuzhiyun ldo2_reg: regulator@4 { 340*4882a593Smuzhiyun regulator-name = "vdd_3v3aux"; 341*4882a593Smuzhiyun regulator-always-on; 342*4882a593Smuzhiyun }; 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun ldo3_reg: regulator@5 { 345*4882a593Smuzhiyun regulator-name = "vdd_1v8"; 346*4882a593Smuzhiyun regulator-always-on; 347*4882a593Smuzhiyun }; 348*4882a593Smuzhiyun 349*4882a593Smuzhiyun ldo4_reg: regulator@6 { 350*4882a593Smuzhiyun regulator-name = "vdd_3v3a"; 351*4882a593Smuzhiyun regulator-always-on; 352*4882a593Smuzhiyun }; 353*4882a593Smuzhiyun }; 354*4882a593Smuzhiyun}; 355*4882a593Smuzhiyun 356*4882a593Smuzhiyun&cpsw_emac0 { 357*4882a593Smuzhiyun phy-handle = <ðphy0>; 358*4882a593Smuzhiyun phy-mode = "mii"; 359*4882a593Smuzhiyun}; 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun&mac { 362*4882a593Smuzhiyun slaves = <1>; 363*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 364*4882a593Smuzhiyun pinctrl-0 = <&cpsw_default>; 365*4882a593Smuzhiyun pinctrl-1 = <&cpsw_sleep>; 366*4882a593Smuzhiyun status = "okay"; 367*4882a593Smuzhiyun}; 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun&davinci_mdio { 370*4882a593Smuzhiyun pinctrl-names = "default", "sleep"; 371*4882a593Smuzhiyun pinctrl-0 = <&davinci_mdio_default>; 372*4882a593Smuzhiyun pinctrl-1 = <&davinci_mdio_sleep>; 373*4882a593Smuzhiyun status = "okay"; 374*4882a593Smuzhiyun 375*4882a593Smuzhiyun ethphy0: ethernet-phy@0 { 376*4882a593Smuzhiyun reg = <0>; 377*4882a593Smuzhiyun }; 378*4882a593Smuzhiyun}; 379*4882a593Smuzhiyun 380*4882a593Smuzhiyun&mmc1 { 381*4882a593Smuzhiyun status = "okay"; 382*4882a593Smuzhiyun bus-width = <0x4>; 383*4882a593Smuzhiyun pinctrl-names = "default"; 384*4882a593Smuzhiyun pinctrl-0 = <&mmc1_pins>; 385*4882a593Smuzhiyun cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; 386*4882a593Smuzhiyun}; 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun&aes { 389*4882a593Smuzhiyun status = "okay"; 390*4882a593Smuzhiyun}; 391*4882a593Smuzhiyun 392*4882a593Smuzhiyun&sham { 393*4882a593Smuzhiyun status = "okay"; 394*4882a593Smuzhiyun}; 395*4882a593Smuzhiyun 396*4882a593Smuzhiyun&rtc { 397*4882a593Smuzhiyun clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; 398*4882a593Smuzhiyun clock-names = "ext-clk", "int-clk"; 399*4882a593Smuzhiyun}; 400