1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * am335x-base0033.dts - Device Tree file for IGEP AQUILA EXPANSION 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include "am335x-igep0033.dtsi" 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/ { 11*4882a593Smuzhiyun model = "IGEP COM AM335x on AQUILA Expansion"; 12*4882a593Smuzhiyun compatible = "isee,am335x-base0033", "isee,am335x-igep0033", "ti,am33xx"; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun hdmi { 15*4882a593Smuzhiyun compatible = "ti,tilcdc,slave"; 16*4882a593Smuzhiyun i2c = <&i2c0>; 17*4882a593Smuzhiyun pinctrl-names = "default", "off"; 18*4882a593Smuzhiyun pinctrl-0 = <&nxp_hdmi_pins>; 19*4882a593Smuzhiyun pinctrl-1 = <&nxp_hdmi_off_pins>; 20*4882a593Smuzhiyun status = "okay"; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun leds_base { 24*4882a593Smuzhiyun pinctrl-names = "default"; 25*4882a593Smuzhiyun pinctrl-0 = <&leds_base_pins>; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun compatible = "gpio-leds"; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun led0 { 30*4882a593Smuzhiyun label = "base:red:user"; 31*4882a593Smuzhiyun gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; /* gpio1_21 */ 32*4882a593Smuzhiyun default-state = "off"; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun led1 { 36*4882a593Smuzhiyun label = "base:green:user"; 37*4882a593Smuzhiyun gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; /* gpio2_0 */ 38*4882a593Smuzhiyun default-state = "off"; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun}; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun&am33xx_pinmux { 44*4882a593Smuzhiyun nxp_hdmi_pins: pinmux_nxp_hdmi_pins { 45*4882a593Smuzhiyun pinctrl-single,pins = < 46*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3) /* xdma_event_intr0.clkout1 */ 47*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) 48*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) 49*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) 50*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) 51*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) 52*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) 53*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) 54*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) 55*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) 56*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) 57*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) 58*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) 59*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) 60*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) 61*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) 62*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) 63*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) 64*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) 65*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) 66*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) 67*4882a593Smuzhiyun >; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun nxp_hdmi_off_pins: pinmux_nxp_hdmi_off_pins { 70*4882a593Smuzhiyun pinctrl-single,pins = < 71*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3) /* xdma_event_intr0.clkout1 */ 72*4882a593Smuzhiyun >; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun leds_base_pins: pinmux_leds_base_pins { 76*4882a593Smuzhiyun pinctrl-single,pins = < 77*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ 78*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_csn3.gpio2_0 */ 79*4882a593Smuzhiyun >; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun}; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun&lcdc { 84*4882a593Smuzhiyun status = "okay"; 85*4882a593Smuzhiyun}; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun&i2c0 { 88*4882a593Smuzhiyun eeprom: eeprom@50 { 89*4882a593Smuzhiyun compatible = "atmel,24c256"; 90*4882a593Smuzhiyun reg = <0x50>; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun}; 93