1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/* 7*4882a593Smuzhiyun * VScom OnRISC 8*4882a593Smuzhiyun * http://www.vscom.de 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/dts-v1/; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun#include "am335x-baltos.dtsi" 14*4882a593Smuzhiyun#include "am335x-baltos-leds.dtsi" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun/ { 17*4882a593Smuzhiyun model = "OnRISC Baltos iR 5221"; 18*4882a593Smuzhiyun}; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun&am33xx_pinmux { 21*4882a593Smuzhiyun tca6416_pins: pinmux_tca6416_pins { 22*4882a593Smuzhiyun pinctrl-single,pins = < 23*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT_PULLUP, MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */ 24*4882a593Smuzhiyun >; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun dcan1_pins: pinmux_dcan1_pins { 29*4882a593Smuzhiyun pinctrl-single,pins = < 30*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart0_ctsn.dcan1_tx_mux0 */ 31*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* uart0_rtsn.dcan1_rx_mux0 */ 32*4882a593Smuzhiyun >; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun uart1_pins: pinmux_uart1_pins { 36*4882a593Smuzhiyun pinctrl-single,pins = < 37*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) 38*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) 39*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) 40*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 41*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */ 42*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */ 43*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */ 44*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */ 45*4882a593Smuzhiyun >; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun uart2_pins: pinmux_uart2_pins { 49*4882a593Smuzhiyun pinctrl-single,pins = < 50*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* spi0_sclk.uart2_rxd_mux3 */ 51*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd_mux3 */ 52*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE2) /* i2c0_sda.uart2_ctsn_mux0 */ 53*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* i2c0_scl.uart2_rtsn_mux0 */ 54*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad12.gpio1[12] DTR */ 55*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad13.gpio1[13] DSR */ 56*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad14.gpio1[14] DCD */ 57*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad15.gpio1[15] RI */ 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */ 60*4882a593Smuzhiyun >; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun mmc1_pins: pinmux_mmc1_pins { 64*4882a593Smuzhiyun pinctrl-single,pins = < 65*4882a593Smuzhiyun AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE7) /* MMC1 CD */ 66*4882a593Smuzhiyun >; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun}; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun&uart1 { 71*4882a593Smuzhiyun pinctrl-names = "default"; 72*4882a593Smuzhiyun pinctrl-0 = <&uart1_pins>; 73*4882a593Smuzhiyun dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; 74*4882a593Smuzhiyun dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; 75*4882a593Smuzhiyun dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; 76*4882a593Smuzhiyun rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun status = "okay"; 79*4882a593Smuzhiyun}; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun&uart2 { 82*4882a593Smuzhiyun pinctrl-names = "default"; 83*4882a593Smuzhiyun pinctrl-0 = <&uart2_pins>; 84*4882a593Smuzhiyun dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; 85*4882a593Smuzhiyun dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; 86*4882a593Smuzhiyun dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; 87*4882a593Smuzhiyun rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun status = "okay"; 90*4882a593Smuzhiyun}; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun&i2c1 { 93*4882a593Smuzhiyun tca6416: gpio@20 { 94*4882a593Smuzhiyun compatible = "ti,tca6416"; 95*4882a593Smuzhiyun reg = <0x20>; 96*4882a593Smuzhiyun gpio-controller; 97*4882a593Smuzhiyun #gpio-cells = <2>; 98*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 99*4882a593Smuzhiyun interrupts = <20 IRQ_TYPE_EDGE_RISING>; 100*4882a593Smuzhiyun pinctrl-names = "default"; 101*4882a593Smuzhiyun pinctrl-0 = <&tca6416_pins>; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun}; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun&usb0_phy { 106*4882a593Smuzhiyun status = "okay"; 107*4882a593Smuzhiyun}; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun&usb1_phy { 110*4882a593Smuzhiyun status = "okay"; 111*4882a593Smuzhiyun}; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun&usb0 { 114*4882a593Smuzhiyun status = "okay"; 115*4882a593Smuzhiyun dr_mode = "host"; 116*4882a593Smuzhiyun}; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun&usb1 { 119*4882a593Smuzhiyun status = "okay"; 120*4882a593Smuzhiyun dr_mode = "host"; 121*4882a593Smuzhiyun}; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun&cpsw_emac0 { 124*4882a593Smuzhiyun phy-mode = "rmii"; 125*4882a593Smuzhiyun dual_emac_res_vlan = <1>; 126*4882a593Smuzhiyun fixed-link { 127*4882a593Smuzhiyun speed = <100>; 128*4882a593Smuzhiyun full-duplex; 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun}; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun&cpsw_emac1 { 133*4882a593Smuzhiyun phy-mode = "rgmii-id"; 134*4882a593Smuzhiyun dual_emac_res_vlan = <2>; 135*4882a593Smuzhiyun phy-handle = <&phy1>; 136*4882a593Smuzhiyun}; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun&dcan1 { 139*4882a593Smuzhiyun pinctrl-names = "default"; 140*4882a593Smuzhiyun pinctrl-0 = <&dcan1_pins>; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun status = "okay"; 143*4882a593Smuzhiyun}; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun&mmc1 { 146*4882a593Smuzhiyun pinctrl-names = "default"; 147*4882a593Smuzhiyun pinctrl-0 = <&mmc1_pins>; 148*4882a593Smuzhiyun cd-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>; 149*4882a593Smuzhiyun}; 150