1*4882a593Smuzhiyun/* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * linux/arch/arm/boot/compressed/head-sa1100.S 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 1999 Nicolas Pitre <nico@fluxnic.net> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SA1100 specific tweaks. This is merged into head.S by the linker. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun#include <linux/linkage.h> 12*4882a593Smuzhiyun#include <asm/mach-types.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun .section ".start", "ax" 15*4882a593Smuzhiyun .arch armv4 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun__SA1100_start: 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun @ Preserve r8/r7 i.e. kernel entry values 20*4882a593Smuzhiyun#ifdef CONFIG_SA1100_COLLIE 21*4882a593Smuzhiyun mov r7, #MACH_TYPE_COLLIE 22*4882a593Smuzhiyun#endif 23*4882a593Smuzhiyun#ifdef CONFIG_SA1100_SIMPAD 24*4882a593Smuzhiyun @ UNTIL we've something like an open bootldr 25*4882a593Smuzhiyun mov r7, #MACH_TYPE_SIMPAD @should be 87 26*4882a593Smuzhiyun#endif 27*4882a593Smuzhiyun mrc p15, 0, r0, c1, c0, 0 @ read control reg 28*4882a593Smuzhiyun ands r0, r0, #0x0d 29*4882a593Smuzhiyun beq 99f 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun @ Data cache might be active. 32*4882a593Smuzhiyun @ Be sure to flush kernel binary out of the cache, 33*4882a593Smuzhiyun @ whatever state it is, before it is turned off. 34*4882a593Smuzhiyun @ This is done by fetching through currently executed 35*4882a593Smuzhiyun @ memory to be sure we hit the same cache. 36*4882a593Smuzhiyun bic r2, pc, #0x1f 37*4882a593Smuzhiyun add r3, r2, #0x4000 @ 16 kb is quite enough... 38*4882a593Smuzhiyun1: ldr r0, [r2], #32 39*4882a593Smuzhiyun teq r2, r3 40*4882a593Smuzhiyun bne 1b 41*4882a593Smuzhiyun mcr p15, 0, r0, c7, c10, 4 @ drain WB 42*4882a593Smuzhiyun mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun @ disabling MMU and caches 45*4882a593Smuzhiyun mrc p15, 0, r0, c1, c0, 0 @ read control reg 46*4882a593Smuzhiyun bic r0, r0, #0x0d @ clear WB, DC, MMU 47*4882a593Smuzhiyun bic r0, r0, #0x1000 @ clear Icache 48*4882a593Smuzhiyun mcr p15, 0, r0, c1, c0, 0 49*4882a593Smuzhiyun99: 50