1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 6*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as 7*4882a593Smuzhiyun * published by the Free Software Foundation. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * vineetg: May 2011 10*4882a593Smuzhiyun * -Support single cycle endian-swap insn in ARC700 4.10 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * vineetg: June 2009 13*4882a593Smuzhiyun * -Better htonl implementation (5 instead of 9 ALU instructions) 14*4882a593Smuzhiyun * -Hardware assisted single cycle bswap (Use Case of ARC custom instrn) 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifndef __ASM_ARC_SWAB_H 18*4882a593Smuzhiyun #define __ASM_ARC_SWAB_H 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #include <linux/types.h> 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* Native single cycle endian swap insn */ 23*4882a593Smuzhiyun #ifdef CONFIG_ARC_HAS_SWAPE 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define __arch_swab32(x) \ 26*4882a593Smuzhiyun ({ \ 27*4882a593Smuzhiyun unsigned int tmp = x; \ 28*4882a593Smuzhiyun __asm__( \ 29*4882a593Smuzhiyun " swape %0, %1 \n" \ 30*4882a593Smuzhiyun : "=r" (tmp) \ 31*4882a593Smuzhiyun : "r" (tmp)); \ 32*4882a593Smuzhiyun tmp; \ 33*4882a593Smuzhiyun }) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #else 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* Several ways of Endian-Swap Emulation for ARC 38*4882a593Smuzhiyun * 0: kernel generic 39*4882a593Smuzhiyun * 1: ARC optimised "C" 40*4882a593Smuzhiyun * 2: ARC Custom instruction 41*4882a593Smuzhiyun */ 42*4882a593Smuzhiyun #define ARC_BSWAP_TYPE 1 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #if (ARC_BSWAP_TYPE == 1) /******* Software only ********/ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* The kernel default implementation of htonl is 47*4882a593Smuzhiyun * return x<<24 | x>>24 | 48*4882a593Smuzhiyun * (x & (__u32)0x0000ff00UL)<<8 | (x & (__u32)0x00ff0000UL)>>8; 49*4882a593Smuzhiyun * 50*4882a593Smuzhiyun * This generates 9 instructions on ARC (excluding the ld/st) 51*4882a593Smuzhiyun * 52*4882a593Smuzhiyun * 8051fd8c: ld r3,[r7,20] ; Mem op : Get the value to be swapped 53*4882a593Smuzhiyun * 8051fd98: asl r5,r3,24 ; get 3rd Byte 54*4882a593Smuzhiyun * 8051fd9c: lsr r2,r3,24 ; get 0th Byte 55*4882a593Smuzhiyun * 8051fda0: and r4,r3,0xff00 56*4882a593Smuzhiyun * 8051fda8: asl r4,r4,8 ; get 1st Byte 57*4882a593Smuzhiyun * 8051fdac: and r3,r3,0x00ff0000 58*4882a593Smuzhiyun * 8051fdb4: or r2,r2,r5 ; combine 0th and 3rd Bytes 59*4882a593Smuzhiyun * 8051fdb8: lsr r3,r3,8 ; 2nd Byte at correct place in Dst Reg 60*4882a593Smuzhiyun * 8051fdbc: or r2,r2,r4 ; combine 0,3 Bytes with 1st Byte 61*4882a593Smuzhiyun * 8051fdc0: or r2,r2,r3 ; combine 0,3,1 Bytes with 2nd Byte 62*4882a593Smuzhiyun * 8051fdc4: st r2,[r1,20] ; Mem op : save result back to mem 63*4882a593Smuzhiyun * 64*4882a593Smuzhiyun * Joern suggested a better "C" algorithm which is great since 65*4882a593Smuzhiyun * (1) It is portable to any architecure 66*4882a593Smuzhiyun * (2) At the same time it takes advantage of ARC ISA (rotate intrns) 67*4882a593Smuzhiyun */ 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define __arch_swab32(x) \ 70*4882a593Smuzhiyun ({ unsigned long __in = (x), __tmp; \ 71*4882a593Smuzhiyun __tmp = __in << 8 | __in >> 24; /* ror tmp,in,24 */ \ 72*4882a593Smuzhiyun __in = __in << 24 | __in >> 8; /* ror in,in,8 */ \ 73*4882a593Smuzhiyun __tmp ^= __in; \ 74*4882a593Smuzhiyun __tmp &= 0xff00ff; \ 75*4882a593Smuzhiyun __tmp ^ __in; \ 76*4882a593Smuzhiyun }) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #elif (ARC_BSWAP_TYPE == 2) /* Custom single cycle bswap instruction */ 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define __arch_swab32(x) \ 81*4882a593Smuzhiyun ({ \ 82*4882a593Smuzhiyun unsigned int tmp = x; \ 83*4882a593Smuzhiyun __asm__( \ 84*4882a593Smuzhiyun " .extInstruction bswap, 7, 0x00, SUFFIX_NONE, SYNTAX_2OP \n"\ 85*4882a593Smuzhiyun " bswap %0, %1 \n"\ 86*4882a593Smuzhiyun : "=r" (tmp) \ 87*4882a593Smuzhiyun : "r" (tmp)); \ 88*4882a593Smuzhiyun tmp; \ 89*4882a593Smuzhiyun }) 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #endif /* ARC_BSWAP_TYPE=zzz */ 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #endif /* CONFIG_ARC_HAS_SWAPE */ 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #if !defined(__STRICT_ANSI__) || defined(__KERNEL__) 96*4882a593Smuzhiyun #define __SWAB_64_THRU_32__ 97*4882a593Smuzhiyun #endif 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun #endif 100